LL_RCC_PLLSAI_ConfigDomain_LTDC() function
Configure PLLSAI used for LTDC domain clock (*) value not defined in all devices.
Arguments
Source
PLLM
PLLN
Between 49/50(*) and 432
PLLR
PLLDIVR
Return value
None
Notes
PLL Source and PLLM Divider can be written only when PLL, PLLI2S and PLLSAI(*) are disabled PLLN/PLLR can be written only when PLLSAI is disabled This can be selected for LTDC PLLCFGR PLLM LL_RCC_PLLSAI_ConfigDomain_LTDC\n PLLSAICFGR PLLSAIN LL_RCC_PLLSAI_ConfigDomain_LTDC\n PLLSAICFGR PLLSAIR LL_RCC_PLLSAI_ConfigDomain_LTDC\n DCKCFGR PLLSAIDIVR LL_RCC_PLLSAI_ConfigDomain_LTDC
Location | Text |
stm32f4xx_ll_rcc.h:6310 | __STATIC_INLINE void LL_RCC_PLLSAI_ConfigDomain_LTDC(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR, uint32_t PLLDIVR) |
Data read by LL_RCC_PLLSAI_ConfigDomain_LTDC()
LL_RCC_PLLSAI_ConfigDomain_LTDC()