CodeScopeSTM32 Libraries and SamplesHALFMC_SDRAM_TimingTypeDef

FMC_SDRAM_TimingTypeDef struct

FMC SDRAM Timing parameters structure definition

Syntax

typedef struct { uint32_t LoadToActiveDelay; uint32_t ExitSelfRefreshDelay; uint32_t SelfRefreshTime; uint32_t RowCycleDelay; uint32_t WriteRecoveryTime; uint32_t RPDelay; uint32_t RCDDelay; } FMC_SDRAM_TimingTypeDef;

Fields

LoadToActiveDelay

Defines the delay between a Load Mode Register command and an active or Refresh command in number of memory clock cycles. This parameter can be a value between Min_Data = 1 and Max_Data = 16. Read more...

ExitSelfRefreshDelay

Defines the delay from releasing the self refresh command to issuing the Activate command in number of memory clock cycles. This parameter can be a value between Min_Data = 1 and Max_Data = 16. Read more...

SelfRefreshTime

Defines the minimum Self Refresh period in number of memory clock cycles. This parameter can be a value between Min_Data = 1 and Max_Data = 16. Read more...

RowCycleDelay

Defines the delay between the Refresh command and the Activate command and the delay between two consecutive Refresh commands in number of memory clock cycles. This parameter can be a value between Min_Data = 1 and Max_Data = 16. Read more...

WriteRecoveryTime

Defines the Write recovery Time in number of memory clock cycles. This parameter can be a value between Min_Data = 1 and Max_Data = 16. Read more...

RPDelay

Defines the delay between a Precharge Command and an other command in number of memory clock cycles. This parameter can be a value between Min_Data = 1 and Max_Data = 16. Read more...

RCDDelay

Defines the delay between the Activate Command and a Read/Write command in number of memory clock cycles. This parameter can be a value between Min_Data = 1 and Max_Data = 16. Read more...

Examples

FMC_SDRAM_TimingTypeDef is referenced by 15 libraries and example projects.

References

Location	Referrer	Scope	Text
stm32f4xx_ll_fmc.h:468			typedef struct
stm32f4xx_ll_fmc.h:497			} FMC_SDRAM_TimingTypeDef;
stm32f4xx_hal_sdram.c:172	HAL_SDRAM_Init()::Timing	HAL_SDRAM_Init()	HAL_StatusTypeDef HAL_SDRAM_Init(SDRAM_HandleTypeDef hsdram, FMC_SDRAM_TimingTypeDef Timing)
stm32f4xx_hal_sdram.h:146	HAL_SDRAM_Init()::Timing	HAL_SDRAM_Init()	HAL_StatusTypeDef HAL_SDRAM_Init(SDRAM_HandleTypeDef hsdram, FMC_SDRAM_TimingTypeDef Timing);
stm32f4xx_ll_fmc.c:1244	FMC_SDRAM_Timing_Init()::Timing	FMC_SDRAM_Timing_Init()	FMC_SDRAM_TimingTypeDef *Timing, uint32_t Bank)
stm32f4xx_ll_fmc.h:497	FMC_SDRAM_TimingTypeDef		} FMC_SDRAM_TimingTypeDef;
stm32f4xx_ll_fmc.h:1375	FMC_SDRAM_Timing_Init()::Timing	FMC_SDRAM_Timing_Init()	FMC_SDRAM_TimingTypeDef *Timing, uint32_t Bank);

Type Use

Variables of FMC_SDRAM_TimingTypeDef type

FMC_SDRAM_Timing_Init()::Timing

HAL_SDRAM_Init()::Timing

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FMC_SDRAM_TimingTypeDef

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FMC_SDRAM_TimingTypeDef

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