CMSIS
TIM_SMCR_TS_Pos is only used within CMSIS.
 
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CodeScopeSTM32 Libraries and SamplesCMSISTIM_SMCR_TS_Pos

TIM_SMCR_TS_Pos macro

Syntax

#define TIM_SMCR_TS_Pos (4U)

References

LocationText
stm32f401xc.h:6127
#define TIM_SMCR_TS_Pos (4U)
stm32f401xe.h:6127
#define TIM_SMCR_TS_Pos (4U)
stm32f407xx.h:11994
#define TIM_SMCR_TS_Pos (4U)
stm32f410rx.h:6079
#define TIM_SMCR_TS_Pos (4U)
stm32f410tx.h:6035
#define TIM_SMCR_TS_Pos (4U)
stm32f411xe.h:6158
#define TIM_SMCR_TS_Pos (4U)
stm32f412zx.h:11782
#define TIM_SMCR_TS_Pos (4U)
stm32f413xx.h:12488
#define TIM_SMCR_TS_Pos (4U)
stm32f417xx.h:12274
#define TIM_SMCR_TS_Pos (4U)
stm32f429xx.h:13546
#define TIM_SMCR_TS_Pos (4U)
stm32f439xx.h:13840
#define TIM_SMCR_TS_Pos (4U)
stm32f446xx.h:13223
#define TIM_SMCR_TS_Pos (4U)
stm32f469xx.h:16559
#define TIM_SMCR_TS_Pos (4U)
stm32f479xx.h:16856
#define TIM_SMCR_TS_Pos (4U)
stm32f401xc.h:6128
#define TIM_SMCR_TS_Msk (0x7UL << TIM_SMCR_TS_Pos) /*!< 0x00000070 */
stm32f401xc.h:6130
#define TIM_SMCR_TS_0 (0x1UL << TIM_SMCR_TS_Pos) /*!< 0x0010 */
stm32f401xc.h:6131
#define TIM_SMCR_TS_1 (0x2UL << TIM_SMCR_TS_Pos) /*!< 0x0020 */
stm32f401xc.h:6132
#define TIM_SMCR_TS_2 (0x4UL << TIM_SMCR_TS_Pos) /*!< 0x0040 */
stm32f401xe.h:6128
#define TIM_SMCR_TS_Msk (0x7UL << TIM_SMCR_TS_Pos) /*!< 0x00000070 */
stm32f401xe.h:6130
#define TIM_SMCR_TS_0 (0x1UL << TIM_SMCR_TS_Pos) /*!< 0x0010 */
stm32f401xe.h:6131
#define TIM_SMCR_TS_1 (0x2UL << TIM_SMCR_TS_Pos) /*!< 0x0020 */
stm32f401xe.h:6132
#define TIM_SMCR_TS_2 (0x4UL << TIM_SMCR_TS_Pos) /*!< 0x0040 */
stm32f407xx.h:11995
#define TIM_SMCR_TS_Msk (0x7UL << TIM_SMCR_TS_Pos) /*!< 0x00000070 */
stm32f407xx.h:11997
#define TIM_SMCR_TS_0 (0x1UL << TIM_SMCR_TS_Pos) /*!< 0x0010 */
stm32f407xx.h:11998
#define TIM_SMCR_TS_1 (0x2UL << TIM_SMCR_TS_Pos) /*!< 0x0020 */
stm32f407xx.h:11999
#define TIM_SMCR_TS_2 (0x4UL << TIM_SMCR_TS_Pos) /*!< 0x0040 */
stm32f410rx.h:6080
#define TIM_SMCR_TS_Msk (0x7UL << TIM_SMCR_TS_Pos) /*!< 0x00000070 */
stm32f410rx.h:6082
#define TIM_SMCR_TS_0 (0x1UL << TIM_SMCR_TS_Pos) /*!< 0x0010 */
stm32f410rx.h:6083
#define TIM_SMCR_TS_1 (0x2UL << TIM_SMCR_TS_Pos) /*!< 0x0020 */
stm32f410rx.h:6084
#define TIM_SMCR_TS_2 (0x4UL << TIM_SMCR_TS_Pos) /*!< 0x0040 */
stm32f411xe.h:6159
#define TIM_SMCR_TS_Msk (0x7UL << TIM_SMCR_TS_Pos) /*!< 0x00000070 */
stm32f411xe.h:6161
#define TIM_SMCR_TS_0 (0x1UL << TIM_SMCR_TS_Pos) /*!< 0x0010 */
stm32f411xe.h:6162
#define TIM_SMCR_TS_1 (0x2UL << TIM_SMCR_TS_Pos) /*!< 0x0020 */
stm32f411xe.h:6163
#define TIM_SMCR_TS_2 (0x4UL << TIM_SMCR_TS_Pos) /*!< 0x0040 */
stm32f412zx.h:11783
#define TIM_SMCR_TS_Msk (0x7UL << TIM_SMCR_TS_Pos) /*!< 0x00000070 */
stm32f412zx.h:11785
#define TIM_SMCR_TS_0 (0x1UL << TIM_SMCR_TS_Pos) /*!< 0x0010 */
stm32f412zx.h:11786
#define TIM_SMCR_TS_1 (0x2UL << TIM_SMCR_TS_Pos) /*!< 0x0020 */
stm32f412zx.h:11787
#define TIM_SMCR_TS_2 (0x4UL << TIM_SMCR_TS_Pos) /*!< 0x0040 */
stm32f413xx.h:12489
#define TIM_SMCR_TS_Msk (0x7UL << TIM_SMCR_TS_Pos) /*!< 0x00000070 */
stm32f413xx.h:12491
#define TIM_SMCR_TS_0 (0x1UL << TIM_SMCR_TS_Pos) /*!< 0x0010 */
stm32f413xx.h:12492
#define TIM_SMCR_TS_1 (0x2UL << TIM_SMCR_TS_Pos) /*!< 0x0020 */
stm32f413xx.h:12493
#define TIM_SMCR_TS_2 (0x4UL << TIM_SMCR_TS_Pos) /*!< 0x0040 */
stm32f417xx.h:12275
#define TIM_SMCR_TS_Msk (0x7UL << TIM_SMCR_TS_Pos) /*!< 0x00000070 */
stm32f417xx.h:12277
#define TIM_SMCR_TS_0 (0x1UL << TIM_SMCR_TS_Pos) /*!< 0x0010 */
stm32f417xx.h:12278
#define TIM_SMCR_TS_1 (0x2UL << TIM_SMCR_TS_Pos) /*!< 0x0020 */
stm32f417xx.h:12279
#define TIM_SMCR_TS_2 (0x4UL << TIM_SMCR_TS_Pos) /*!< 0x0040 */
stm32f429xx.h:13547
#define TIM_SMCR_TS_Msk (0x7UL << TIM_SMCR_TS_Pos) /*!< 0x00000070 */
stm32f429xx.h:13549
#define TIM_SMCR_TS_0 (0x1UL << TIM_SMCR_TS_Pos) /*!< 0x0010 */
stm32f429xx.h:13550
#define TIM_SMCR_TS_1 (0x2UL << TIM_SMCR_TS_Pos) /*!< 0x0020 */
stm32f429xx.h:13551
#define TIM_SMCR_TS_2 (0x4UL << TIM_SMCR_TS_Pos) /*!< 0x0040 */
stm32f439xx.h:13841
#define TIM_SMCR_TS_Msk (0x7UL << TIM_SMCR_TS_Pos) /*!< 0x00000070 */
stm32f439xx.h:13843
#define TIM_SMCR_TS_0 (0x1UL << TIM_SMCR_TS_Pos) /*!< 0x0010 */
stm32f439xx.h:13844
#define TIM_SMCR_TS_1 (0x2UL << TIM_SMCR_TS_Pos) /*!< 0x0020 */
stm32f439xx.h:13845
#define TIM_SMCR_TS_2 (0x4UL << TIM_SMCR_TS_Pos) /*!< 0x0040 */
stm32f446xx.h:13224
#define TIM_SMCR_TS_Msk (0x7UL << TIM_SMCR_TS_Pos) /*!< 0x00000070 */
stm32f446xx.h:13226
#define TIM_SMCR_TS_0 (0x1UL << TIM_SMCR_TS_Pos) /*!< 0x0010 */
stm32f446xx.h:13227
#define TIM_SMCR_TS_1 (0x2UL << TIM_SMCR_TS_Pos) /*!< 0x0020 */
stm32f446xx.h:13228
#define TIM_SMCR_TS_2 (0x4UL << TIM_SMCR_TS_Pos) /*!< 0x0040 */
stm32f469xx.h:16560
#define TIM_SMCR_TS_Msk (0x7UL << TIM_SMCR_TS_Pos) /*!< 0x00000070 */
stm32f469xx.h:16562
#define TIM_SMCR_TS_0 (0x1UL << TIM_SMCR_TS_Pos) /*!< 0x0010 */
stm32f469xx.h:16563
#define TIM_SMCR_TS_1 (0x2UL << TIM_SMCR_TS_Pos) /*!< 0x0020 */
stm32f469xx.h:16564
#define TIM_SMCR_TS_2 (0x4UL << TIM_SMCR_TS_Pos) /*!< 0x0040 */
stm32f479xx.h:16857
#define TIM_SMCR_TS_Msk (0x7UL << TIM_SMCR_TS_Pos) /*!< 0x00000070 */
stm32f479xx.h:16859
#define TIM_SMCR_TS_0 (0x1UL << TIM_SMCR_TS_Pos) /*!< 0x0010 */
stm32f479xx.h:16860
#define TIM_SMCR_TS_1 (0x2UL << TIM_SMCR_TS_Pos) /*!< 0x0020 */
stm32f479xx.h:16861
#define TIM_SMCR_TS_2 (0x4UL << TIM_SMCR_TS_Pos) /*!< 0x0040 */