CMSIS
TIM_SMCR_ETPS_Pos is only used within CMSIS.
 
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CodeScopeSTM32 Libraries and SamplesCMSISTIM_SMCR_ETPS_Pos

TIM_SMCR_ETPS_Pos macro

Syntax

#define TIM_SMCR_ETPS_Pos (12U)

References

LocationText
stm32f401xc.h:6146
#define TIM_SMCR_ETPS_Pos (12U)
stm32f401xe.h:6146
#define TIM_SMCR_ETPS_Pos (12U)
stm32f407xx.h:12013
#define TIM_SMCR_ETPS_Pos (12U)
stm32f410rx.h:6098
#define TIM_SMCR_ETPS_Pos (12U)
stm32f410tx.h:6054
#define TIM_SMCR_ETPS_Pos (12U)
stm32f411xe.h:6177
#define TIM_SMCR_ETPS_Pos (12U)
stm32f412zx.h:11801
#define TIM_SMCR_ETPS_Pos (12U)
stm32f413xx.h:12507
#define TIM_SMCR_ETPS_Pos (12U)
stm32f417xx.h:12293
#define TIM_SMCR_ETPS_Pos (12U)
stm32f429xx.h:13565
#define TIM_SMCR_ETPS_Pos (12U)
stm32f439xx.h:13859
#define TIM_SMCR_ETPS_Pos (12U)
stm32f446xx.h:13242
#define TIM_SMCR_ETPS_Pos (12U)
stm32f469xx.h:16578
#define TIM_SMCR_ETPS_Pos (12U)
stm32f479xx.h:16875
#define TIM_SMCR_ETPS_Pos (12U)
stm32f401xc.h:6147
#define TIM_SMCR_ETPS_Msk (0x3UL << TIM_SMCR_ETPS_Pos) /*!< 0x00003000 */
stm32f401xc.h:6149
#define TIM_SMCR_ETPS_0 (0x1UL << TIM_SMCR_ETPS_Pos) /*!< 0x1000 */
stm32f401xc.h:6150
#define TIM_SMCR_ETPS_1 (0x2UL << TIM_SMCR_ETPS_Pos) /*!< 0x2000 */
stm32f401xe.h:6147
#define TIM_SMCR_ETPS_Msk (0x3UL << TIM_SMCR_ETPS_Pos) /*!< 0x00003000 */
stm32f401xe.h:6149
#define TIM_SMCR_ETPS_0 (0x1UL << TIM_SMCR_ETPS_Pos) /*!< 0x1000 */
stm32f401xe.h:6150
#define TIM_SMCR_ETPS_1 (0x2UL << TIM_SMCR_ETPS_Pos) /*!< 0x2000 */
stm32f407xx.h:12014
#define TIM_SMCR_ETPS_Msk (0x3UL << TIM_SMCR_ETPS_Pos) /*!< 0x00003000 */
stm32f407xx.h:12016
#define TIM_SMCR_ETPS_0 (0x1UL << TIM_SMCR_ETPS_Pos) /*!< 0x1000 */
stm32f407xx.h:12017
#define TIM_SMCR_ETPS_1 (0x2UL << TIM_SMCR_ETPS_Pos) /*!< 0x2000 */
stm32f410rx.h:6099
#define TIM_SMCR_ETPS_Msk (0x3UL << TIM_SMCR_ETPS_Pos) /*!< 0x00003000 */
stm32f410rx.h:6101
#define TIM_SMCR_ETPS_0 (0x1UL << TIM_SMCR_ETPS_Pos) /*!< 0x1000 */
stm32f410rx.h:6102
#define TIM_SMCR_ETPS_1 (0x2UL << TIM_SMCR_ETPS_Pos) /*!< 0x2000 */
stm32f411xe.h:6178
#define TIM_SMCR_ETPS_Msk (0x3UL << TIM_SMCR_ETPS_Pos) /*!< 0x00003000 */
stm32f411xe.h:6180
#define TIM_SMCR_ETPS_0 (0x1UL << TIM_SMCR_ETPS_Pos) /*!< 0x1000 */
stm32f411xe.h:6181
#define TIM_SMCR_ETPS_1 (0x2UL << TIM_SMCR_ETPS_Pos) /*!< 0x2000 */
stm32f412zx.h:11802
#define TIM_SMCR_ETPS_Msk (0x3UL << TIM_SMCR_ETPS_Pos) /*!< 0x00003000 */
stm32f412zx.h:11804
#define TIM_SMCR_ETPS_0 (0x1UL << TIM_SMCR_ETPS_Pos) /*!< 0x1000 */
stm32f412zx.h:11805
#define TIM_SMCR_ETPS_1 (0x2UL << TIM_SMCR_ETPS_Pos) /*!< 0x2000 */
stm32f413xx.h:12508
#define TIM_SMCR_ETPS_Msk (0x3UL << TIM_SMCR_ETPS_Pos) /*!< 0x00003000 */
stm32f413xx.h:12510
#define TIM_SMCR_ETPS_0 (0x1UL << TIM_SMCR_ETPS_Pos) /*!< 0x1000 */
stm32f413xx.h:12511
#define TIM_SMCR_ETPS_1 (0x2UL << TIM_SMCR_ETPS_Pos) /*!< 0x2000 */
stm32f417xx.h:12294
#define TIM_SMCR_ETPS_Msk (0x3UL << TIM_SMCR_ETPS_Pos) /*!< 0x00003000 */
stm32f417xx.h:12296
#define TIM_SMCR_ETPS_0 (0x1UL << TIM_SMCR_ETPS_Pos) /*!< 0x1000 */
stm32f417xx.h:12297
#define TIM_SMCR_ETPS_1 (0x2UL << TIM_SMCR_ETPS_Pos) /*!< 0x2000 */
stm32f429xx.h:13566
#define TIM_SMCR_ETPS_Msk (0x3UL << TIM_SMCR_ETPS_Pos) /*!< 0x00003000 */
stm32f429xx.h:13568
#define TIM_SMCR_ETPS_0 (0x1UL << TIM_SMCR_ETPS_Pos) /*!< 0x1000 */
stm32f429xx.h:13569
#define TIM_SMCR_ETPS_1 (0x2UL << TIM_SMCR_ETPS_Pos) /*!< 0x2000 */
stm32f439xx.h:13860
#define TIM_SMCR_ETPS_Msk (0x3UL << TIM_SMCR_ETPS_Pos) /*!< 0x00003000 */
stm32f439xx.h:13862
#define TIM_SMCR_ETPS_0 (0x1UL << TIM_SMCR_ETPS_Pos) /*!< 0x1000 */
stm32f439xx.h:13863
#define TIM_SMCR_ETPS_1 (0x2UL << TIM_SMCR_ETPS_Pos) /*!< 0x2000 */
stm32f446xx.h:13243
#define TIM_SMCR_ETPS_Msk (0x3UL << TIM_SMCR_ETPS_Pos) /*!< 0x00003000 */
stm32f446xx.h:13245
#define TIM_SMCR_ETPS_0 (0x1UL << TIM_SMCR_ETPS_Pos) /*!< 0x1000 */
stm32f446xx.h:13246
#define TIM_SMCR_ETPS_1 (0x2UL << TIM_SMCR_ETPS_Pos) /*!< 0x2000 */
stm32f469xx.h:16579
#define TIM_SMCR_ETPS_Msk (0x3UL << TIM_SMCR_ETPS_Pos) /*!< 0x00003000 */
stm32f469xx.h:16581
#define TIM_SMCR_ETPS_0 (0x1UL << TIM_SMCR_ETPS_Pos) /*!< 0x1000 */
stm32f469xx.h:16582
#define TIM_SMCR_ETPS_1 (0x2UL << TIM_SMCR_ETPS_Pos) /*!< 0x2000 */
stm32f479xx.h:16876
#define TIM_SMCR_ETPS_Msk (0x3UL << TIM_SMCR_ETPS_Pos) /*!< 0x00003000 */
stm32f479xx.h:16878
#define TIM_SMCR_ETPS_0 (0x1UL << TIM_SMCR_ETPS_Pos) /*!< 0x1000 */
stm32f479xx.h:16879
#define TIM_SMCR_ETPS_1 (0x2UL << TIM_SMCR_ETPS_Pos) /*!< 0x2000 */