CMSIS
SPI_CR1_BR_Pos is only used within CMSIS.
 
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CodeScopeSTM32 Libraries and SamplesCMSISSPI_CR1_BR_Pos

SPI_CR1_BR_Pos macro

Syntax

#define SPI_CR1_BR_Pos (3U)

References

LocationText
stm32f401xc.h:5640
#define SPI_CR1_BR_Pos (3U)
stm32f401xe.h:5640
#define SPI_CR1_BR_Pos (3U)
stm32f407xx.h:11461
#define SPI_CR1_BR_Pos (3U)
stm32f410rx.h:5609
#define SPI_CR1_BR_Pos (3U)
stm32f410tx.h:5565
#define SPI_CR1_BR_Pos (3U)
stm32f411xe.h:5671
#define SPI_CR1_BR_Pos (3U)
stm32f412zx.h:11252
#define SPI_CR1_BR_Pos (3U)
stm32f413xx.h:11893
#define SPI_CR1_BR_Pos (3U)
stm32f417xx.h:11743
#define SPI_CR1_BR_Pos (3U)
stm32f429xx.h:12962
#define SPI_CR1_BR_Pos (3U)
stm32f439xx.h:13256
#define SPI_CR1_BR_Pos (3U)
stm32f446xx.h:12633
#define SPI_CR1_BR_Pos (3U)
stm32f469xx.h:15974
#define SPI_CR1_BR_Pos (3U)
stm32f479xx.h:16271
#define SPI_CR1_BR_Pos (3U)
stm32f401xc.h:5641
#define SPI_CR1_BR_Msk (0x7UL << SPI_CR1_BR_Pos) /*!< 0x00000038 */
stm32f401xc.h:5643
#define SPI_CR1_BR_0 (0x1UL << SPI_CR1_BR_Pos) /*!< 0x00000008 */
stm32f401xc.h:5644
#define SPI_CR1_BR_1 (0x2UL << SPI_CR1_BR_Pos) /*!< 0x00000010 */
stm32f401xc.h:5645
#define SPI_CR1_BR_2 (0x4UL << SPI_CR1_BR_Pos) /*!< 0x00000020 */
stm32f401xe.h:5641
#define SPI_CR1_BR_Msk (0x7UL << SPI_CR1_BR_Pos) /*!< 0x00000038 */
stm32f401xe.h:5644
#define SPI_CR1_BR_1 (0x2UL << SPI_CR1_BR_Pos) /*!< 0x00000010 */
stm32f407xx.h:11462
#define SPI_CR1_BR_Msk (0x7UL << SPI_CR1_BR_Pos) /*!< 0x00000038 */
stm32f407xx.h:11464
#define SPI_CR1_BR_0 (0x1UL << SPI_CR1_BR_Pos) /*!< 0x00000008 */
stm32f407xx.h:11465
#define SPI_CR1_BR_1 (0x2UL << SPI_CR1_BR_Pos) /*!< 0x00000010 */
stm32f407xx.h:11466
#define SPI_CR1_BR_2 (0x4UL << SPI_CR1_BR_Pos) /*!< 0x00000020 */
stm32f410rx.h:5610
#define SPI_CR1_BR_Msk (0x7UL << SPI_CR1_BR_Pos) /*!< 0x00000038 */
stm32f410rx.h:5613
#define SPI_CR1_BR_1 (0x2UL << SPI_CR1_BR_Pos) /*!< 0x00000010 */
stm32f411xe.h:5672
#define SPI_CR1_BR_Msk (0x7UL << SPI_CR1_BR_Pos) /*!< 0x00000038 */
stm32f411xe.h:5674
#define SPI_CR1_BR_0 (0x1UL << SPI_CR1_BR_Pos) /*!< 0x00000008 */
stm32f411xe.h:5675
#define SPI_CR1_BR_1 (0x2UL << SPI_CR1_BR_Pos) /*!< 0x00000010 */
stm32f411xe.h:5676
#define SPI_CR1_BR_2 (0x4UL << SPI_CR1_BR_Pos) /*!< 0x00000020 */
stm32f412zx.h:11253
#define SPI_CR1_BR_Msk (0x7UL << SPI_CR1_BR_Pos) /*!< 0x00000038 */
stm32f412zx.h:11255
#define SPI_CR1_BR_0 (0x1UL << SPI_CR1_BR_Pos) /*!< 0x00000008 */
stm32f412zx.h:11256
#define SPI_CR1_BR_1 (0x2UL << SPI_CR1_BR_Pos) /*!< 0x00000010 */
stm32f412zx.h:11257
#define SPI_CR1_BR_2 (0x4UL << SPI_CR1_BR_Pos) /*!< 0x00000020 */
stm32f413xx.h:11894
#define SPI_CR1_BR_Msk (0x7UL << SPI_CR1_BR_Pos) /*!< 0x00000038 */
stm32f413xx.h:11896
#define SPI_CR1_BR_0 (0x1UL << SPI_CR1_BR_Pos) /*!< 0x00000008 */
stm32f413xx.h:11897
#define SPI_CR1_BR_1 (0x2UL << SPI_CR1_BR_Pos) /*!< 0x00000010 */
stm32f413xx.h:11898
#define SPI_CR1_BR_2 (0x4UL << SPI_CR1_BR_Pos) /*!< 0x00000020 */
stm32f429xx.h:12963
#define SPI_CR1_BR_Msk (0x7UL << SPI_CR1_BR_Pos) /*!< 0x00000038 */
stm32f429xx.h:12965
#define SPI_CR1_BR_0 (0x1UL << SPI_CR1_BR_Pos) /*!< 0x00000008 */
stm32f429xx.h:12966
#define SPI_CR1_BR_1 (0x2UL << SPI_CR1_BR_Pos) /*!< 0x00000010 */
stm32f429xx.h:12967
#define SPI_CR1_BR_2 (0x4UL << SPI_CR1_BR_Pos) /*!< 0x00000020 */
stm32f446xx.h:12634
#define SPI_CR1_BR_Msk (0x7UL << SPI_CR1_BR_Pos) /*!< 0x00000038 */
stm32f446xx.h:12636
#define SPI_CR1_BR_0 (0x1UL << SPI_CR1_BR_Pos) /*!< 0x00000008 */
stm32f446xx.h:12637
#define SPI_CR1_BR_1 (0x2UL << SPI_CR1_BR_Pos) /*!< 0x00000010 */
stm32f446xx.h:12638
#define SPI_CR1_BR_2 (0x4UL << SPI_CR1_BR_Pos) /*!< 0x00000020 */
stm32f469xx.h:15975
#define SPI_CR1_BR_Msk (0x7UL << SPI_CR1_BR_Pos) /*!< 0x00000038 */
stm32f469xx.h:15977
#define SPI_CR1_BR_0 (0x1UL << SPI_CR1_BR_Pos) /*!< 0x00000008 */
stm32f469xx.h:15978
#define SPI_CR1_BR_1 (0x2UL << SPI_CR1_BR_Pos) /*!< 0x00000010 */
stm32f469xx.h:15979
#define SPI_CR1_BR_2 (0x4UL << SPI_CR1_BR_Pos) /*!< 0x00000020 */