CMSIS
RCC_CFGR_SW_Pos is only used within CMSIS.
 
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CodeScopeSTM32 Libraries and SamplesCMSISRCC_CFGR_SW_Pos

RCC_CFGR_SW_Pos macro

Bit definition for RCC_CFGR register *****************

Syntax

#define RCC_CFGR_SW_Pos (0U)

References

LocationText
stm32f401xc.h:3978
#define RCC_CFGR_SW_Pos (0U)
stm32f401xe.h:3978
#define RCC_CFGR_SW_Pos (0U)
stm32f407xx.h:9544
#define RCC_CFGR_SW_Pos (0U)
stm32f410rx.h:4326
#define RCC_CFGR_SW_Pos (0U)
stm32f410tx.h:4316
#define RCC_CFGR_SW_Pos (0U)
stm32f411xe.h:3987
#define RCC_CFGR_SW_Pos (0U)
stm32f412zx.h:9341
#define RCC_CFGR_SW_Pos (0U)
stm32f413xx.h:9575
#define RCC_CFGR_SW_Pos (0U)
stm32f417xx.h:9806
#define RCC_CFGR_SW_Pos (0U)
stm32f429xx.h:10607
#define RCC_CFGR_SW_Pos (0U)
stm32f439xx.h:10881
#define RCC_CFGR_SW_Pos (0U)
stm32f446xx.h:10158
#define RCC_CFGR_SW_Pos (0U)
stm32f469xx.h:13611
#define RCC_CFGR_SW_Pos (0U)
stm32f479xx.h:13888
#define RCC_CFGR_SW_Pos (0U)
stm32f401xc.h:3979
#define RCC_CFGR_SW_Msk (0x3UL << RCC_CFGR_SW_Pos) /*!< 0x00000003 */
stm32f401xc.h:3981
#define RCC_CFGR_SW_0 (0x1UL << RCC_CFGR_SW_Pos) /*!< 0x00000001 */
stm32f401xc.h:3982
#define RCC_CFGR_SW_1 (0x2UL << RCC_CFGR_SW_Pos) /*!< 0x00000002 */
stm32f401xe.h:3979
#define RCC_CFGR_SW_Msk (0x3UL << RCC_CFGR_SW_Pos) /*!< 0x00000003 */
stm32f401xe.h:3981
#define RCC_CFGR_SW_0 (0x1UL << RCC_CFGR_SW_Pos) /*!< 0x00000001 */
stm32f401xe.h:3982
#define RCC_CFGR_SW_1 (0x2UL << RCC_CFGR_SW_Pos) /*!< 0x00000002 */
stm32f407xx.h:9545
#define RCC_CFGR_SW_Msk (0x3UL << RCC_CFGR_SW_Pos) /*!< 0x00000003 */
stm32f407xx.h:9547
#define RCC_CFGR_SW_0 (0x1UL << RCC_CFGR_SW_Pos) /*!< 0x00000001 */
stm32f407xx.h:9548
#define RCC_CFGR_SW_1 (0x2UL << RCC_CFGR_SW_Pos) /*!< 0x00000002 */
stm32f410rx.h:4327
#define RCC_CFGR_SW_Msk (0x3UL << RCC_CFGR_SW_Pos) /*!< 0x00000003 */
stm32f410rx.h:4329
#define RCC_CFGR_SW_0 (0x1UL << RCC_CFGR_SW_Pos) /*!< 0x00000001 */
stm32f410rx.h:4330
#define RCC_CFGR_SW_1 (0x2UL << RCC_CFGR_SW_Pos) /*!< 0x00000002 */
stm32f410tx.h:4317
#define RCC_CFGR_SW_Msk (0x3UL << RCC_CFGR_SW_Pos) /*!< 0x00000003 */
stm32f411xe.h:3988
#define RCC_CFGR_SW_Msk (0x3UL << RCC_CFGR_SW_Pos) /*!< 0x00000003 */
stm32f411xe.h:3990
#define RCC_CFGR_SW_0 (0x1UL << RCC_CFGR_SW_Pos) /*!< 0x00000001 */
stm32f411xe.h:3991
#define RCC_CFGR_SW_1 (0x2UL << RCC_CFGR_SW_Pos) /*!< 0x00000002 */
stm32f412zx.h:9342
#define RCC_CFGR_SW_Msk (0x3UL << RCC_CFGR_SW_Pos) /*!< 0x00000003 */
stm32f412zx.h:9344
#define RCC_CFGR_SW_0 (0x1UL << RCC_CFGR_SW_Pos) /*!< 0x00000001 */
stm32f412zx.h:9345
#define RCC_CFGR_SW_1 (0x2UL << RCC_CFGR_SW_Pos) /*!< 0x00000002 */
stm32f413xx.h:9576
#define RCC_CFGR_SW_Msk (0x3UL << RCC_CFGR_SW_Pos) /*!< 0x00000003 */
stm32f413xx.h:9578
#define RCC_CFGR_SW_0 (0x1UL << RCC_CFGR_SW_Pos) /*!< 0x00000001 */
stm32f413xx.h:9579
#define RCC_CFGR_SW_1 (0x2UL << RCC_CFGR_SW_Pos) /*!< 0x00000002 */
stm32f417xx.h:9807
#define RCC_CFGR_SW_Msk (0x3UL << RCC_CFGR_SW_Pos) /*!< 0x00000003 */
stm32f417xx.h:9809
#define RCC_CFGR_SW_0 (0x1UL << RCC_CFGR_SW_Pos) /*!< 0x00000001 */
stm32f417xx.h:9810
#define RCC_CFGR_SW_1 (0x2UL << RCC_CFGR_SW_Pos) /*!< 0x00000002 */
stm32f429xx.h:10608
#define RCC_CFGR_SW_Msk (0x3UL << RCC_CFGR_SW_Pos) /*!< 0x00000003 */
stm32f429xx.h:10610
#define RCC_CFGR_SW_0 (0x1UL << RCC_CFGR_SW_Pos) /*!< 0x00000001 */
stm32f429xx.h:10611
#define RCC_CFGR_SW_1 (0x2UL << RCC_CFGR_SW_Pos) /*!< 0x00000002 */
stm32f439xx.h:10882
#define RCC_CFGR_SW_Msk (0x3UL << RCC_CFGR_SW_Pos) /*!< 0x00000003 */
stm32f439xx.h:10884
#define RCC_CFGR_SW_0 (0x1UL << RCC_CFGR_SW_Pos) /*!< 0x00000001 */
stm32f439xx.h:10885
#define RCC_CFGR_SW_1 (0x2UL << RCC_CFGR_SW_Pos) /*!< 0x00000002 */
stm32f446xx.h:10159
#define RCC_CFGR_SW_Msk (0x3UL << RCC_CFGR_SW_Pos) /*!< 0x00000003 */
stm32f446xx.h:10161
#define RCC_CFGR_SW_0 (0x1UL << RCC_CFGR_SW_Pos) /*!< 0x00000001 */
stm32f446xx.h:10162
#define RCC_CFGR_SW_1 (0x2UL << RCC_CFGR_SW_Pos) /*!< 0x00000002 */
stm32f469xx.h:13612
#define RCC_CFGR_SW_Msk (0x3UL << RCC_CFGR_SW_Pos) /*!< 0x00000003 */
stm32f469xx.h:13614
#define RCC_CFGR_SW_0 (0x1UL << RCC_CFGR_SW_Pos) /*!< 0x00000001 */
stm32f469xx.h:13615
#define RCC_CFGR_SW_1 (0x2UL << RCC_CFGR_SW_Pos) /*!< 0x00000002 */
stm32f479xx.h:13889
#define RCC_CFGR_SW_Msk (0x3UL << RCC_CFGR_SW_Pos) /*!< 0x00000003 */
stm32f479xx.h:13891
#define RCC_CFGR_SW_0 (0x1UL << RCC_CFGR_SW_Pos) /*!< 0x00000001 */
stm32f479xx.h:13892
#define RCC_CFGR_SW_1 (0x2UL << RCC_CFGR_SW_Pos) /*!< 0x00000002 */