CMSIS
FMC_BWTR1_ADDHLD_Msk is only used within CMSIS.
 
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CodeScopeSTM32 Libraries and SamplesCMSISFMC_BWTR1_ADDHLD_Msk

FMC_BWTR1_ADDHLD_Msk macro

0x000000F0

Syntax

#define FMC_BWTR1_ADDHLD_Msk (0xFUL << FMC_BWTR1_ADDHLD_Pos)

References

LocationText
stm32f429xx.h:7780
#define FMC_BWTR1_ADDHLD_Msk (0xFUL << FMC_BWTR1_ADDHLD_Pos) /*!< 0x000000F0 */
stm32f439xx.h:7967
#define FMC_BWTR1_ADDHLD_Msk (0xFUL << FMC_BWTR1_ADDHLD_Pos) /*!< 0x000000F0 */
stm32f446xx.h:7490
#define FMC_BWTR1_ADDHLD_Msk (0xFUL << FMC_BWTR1_ADDHLD_Pos) /*!< 0x000000F0 */
stm32f469xx.h:10930
#define FMC_BWTR1_ADDHLD_Msk (0xFUL << FMC_BWTR1_ADDHLD_Pos) /*!< 0x000000F0 */
stm32f479xx.h:11120
#define FMC_BWTR1_ADDHLD_Msk (0xFUL << FMC_BWTR1_ADDHLD_Pos) /*!< 0x000000F0 */
stm32f429xx.h:7781
#define FMC_BWTR1_ADDHLD FMC_BWTR1_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
stm32f439xx.h:7968
#define FMC_BWTR1_ADDHLD FMC_BWTR1_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
stm32f446xx.h:7491
#define FMC_BWTR1_ADDHLD FMC_BWTR1_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
stm32f469xx.h:10931
#define FMC_BWTR1_ADDHLD FMC_BWTR1_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
stm32f479xx.h:11121
#define FMC_BWTR1_ADDHLD FMC_BWTR1_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */