CMSIS
DMA2_BASE is only used within CMSIS.
 
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CodeScopeSTM32 Libraries and SamplesCMSISDMA2_BASE

DMA2_BASE macro

Syntax

#define DMA2_BASE (AHB1PERIPH_BASE + 0x6400UL)

References

LocationText
stm32f401xc.h:709
#define DMA2_BASE (AHB1PERIPH_BASE + 0x6400UL)
stm32f401xe.h:709
#define DMA2_BASE (AHB1PERIPH_BASE + 0x6400UL)
stm32f407xx.h:1002
#define DMA2_BASE (AHB1PERIPH_BASE + 0x6400UL)
stm32f410rx.h:627
#define DMA2_BASE (AHB1PERIPH_BASE + 0x6400UL)
stm32f410tx.h:620
#define DMA2_BASE (AHB1PERIPH_BASE + 0x6400UL)
stm32f411xe.h:711
#define DMA2_BASE (AHB1PERIPH_BASE + 0x6400UL)
stm32f412zx.h:932
#define DMA2_BASE (AHB1PERIPH_BASE + 0x6400UL)
stm32f413xx.h:1036
#define DMA2_BASE (AHB1PERIPH_BASE + 0x6400UL)
stm32f417xx.h:1070
#define DMA2_BASE (AHB1PERIPH_BASE + 0x6400UL)
stm32f429xx.h:1135
#define DMA2_BASE (AHB1PERIPH_BASE + 0x6400UL)
stm32f439xx.h:1205
#define DMA2_BASE (AHB1PERIPH_BASE + 0x6400UL)
stm32f446xx.h:1019
#define DMA2_BASE (AHB1PERIPH_BASE + 0x6400UL)
stm32f469xx.h:1226
#define DMA2_BASE (AHB1PERIPH_BASE + 0x6400UL)
stm32f479xx.h:1296
#define DMA2_BASE (AHB1PERIPH_BASE + 0x6400UL)
stm32f401xc.h:710
#define DMA2_Stream0_BASE (DMA2_BASE + 0x010UL)
stm32f401xc.h:711
#define DMA2_Stream1_BASE (DMA2_BASE + 0x028UL)
stm32f401xc.h:712
#define DMA2_Stream2_BASE (DMA2_BASE + 0x040UL)
stm32f401xc.h:713
#define DMA2_Stream3_BASE (DMA2_BASE + 0x058UL)
stm32f401xc.h:714
#define DMA2_Stream4_BASE (DMA2_BASE + 0x070UL)
stm32f401xc.h:715
#define DMA2_Stream5_BASE (DMA2_BASE + 0x088UL)
stm32f401xc.h:716
#define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0UL)
stm32f401xc.h:797
#define DMA2 ((DMA_TypeDef *) DMA2_BASE)
stm32f401xe.h:710
#define DMA2_Stream0_BASE (DMA2_BASE + 0x010UL)
stm32f401xe.h:711
#define DMA2_Stream1_BASE (DMA2_BASE + 0x028UL)
stm32f401xe.h:712
#define DMA2_Stream2_BASE (DMA2_BASE + 0x040UL)
stm32f401xe.h:713
#define DMA2_Stream3_BASE (DMA2_BASE + 0x058UL)
stm32f401xe.h:714
#define DMA2_Stream4_BASE (DMA2_BASE + 0x070UL)
stm32f401xe.h:715
#define DMA2_Stream5_BASE (DMA2_BASE + 0x088UL)
stm32f401xe.h:716
#define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0UL)
stm32f401xe.h:797
#define DMA2 ((DMA_TypeDef *) DMA2_BASE)
stm32f407xx.h:1003
#define DMA2_Stream0_BASE (DMA2_BASE + 0x010UL)
stm32f407xx.h:1004
#define DMA2_Stream1_BASE (DMA2_BASE + 0x028UL)
stm32f407xx.h:1005
#define DMA2_Stream2_BASE (DMA2_BASE + 0x040UL)
stm32f407xx.h:1006
#define DMA2_Stream3_BASE (DMA2_BASE + 0x058UL)
stm32f407xx.h:1007
#define DMA2_Stream4_BASE (DMA2_BASE + 0x070UL)
stm32f407xx.h:1008
#define DMA2_Stream5_BASE (DMA2_BASE + 0x088UL)
stm32f407xx.h:1009
#define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0UL)
stm32f407xx.h:1010
#define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8UL)
stm32f407xx.h:1123
#define DMA2 ((DMA_TypeDef *) DMA2_BASE)
stm32f410rx.h:628
#define DMA2_Stream0_BASE (DMA2_BASE + 0x010UL)
stm32f410rx.h:629
#define DMA2_Stream1_BASE (DMA2_BASE + 0x028UL)
stm32f410rx.h:630
#define DMA2_Stream2_BASE (DMA2_BASE + 0x040UL)
stm32f410rx.h:631
#define DMA2_Stream3_BASE (DMA2_BASE + 0x058UL)
stm32f410rx.h:632
#define DMA2_Stream4_BASE (DMA2_BASE + 0x070UL)
stm32f410rx.h:633
#define DMA2_Stream5_BASE (DMA2_BASE + 0x088UL)
stm32f410rx.h:634
#define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0UL)
stm32f410rx.h:635
#define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8UL)
stm32f410rx.h:695
#define DMA2 ((DMA_TypeDef *) DMA2_BASE)
stm32f411xe.h:712
#define DMA2_Stream0_BASE (DMA2_BASE + 0x010UL)
stm32f411xe.h:713
#define DMA2_Stream1_BASE (DMA2_BASE + 0x028UL)
stm32f411xe.h:714
#define DMA2_Stream2_BASE (DMA2_BASE + 0x040UL)
stm32f411xe.h:715
#define DMA2_Stream3_BASE (DMA2_BASE + 0x058UL)
stm32f411xe.h:716
#define DMA2_Stream4_BASE (DMA2_BASE + 0x070UL)
stm32f411xe.h:717
#define DMA2_Stream5_BASE (DMA2_BASE + 0x088UL)
stm32f411xe.h:718
#define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0UL)
stm32f411xe.h:719
#define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8UL)
stm32f411xe.h:800
#define DMA2 ((DMA_TypeDef *) DMA2_BASE)
stm32f412zx.h:933
#define DMA2_Stream0_BASE (DMA2_BASE + 0x010UL)
stm32f412zx.h:934
#define DMA2_Stream1_BASE (DMA2_BASE + 0x028UL)
stm32f412zx.h:935
#define DMA2_Stream2_BASE (DMA2_BASE + 0x040UL)
stm32f412zx.h:936
#define DMA2_Stream3_BASE (DMA2_BASE + 0x058UL)
stm32f412zx.h:937
#define DMA2_Stream4_BASE (DMA2_BASE + 0x070UL)
stm32f412zx.h:938
#define DMA2_Stream5_BASE (DMA2_BASE + 0x088UL)
stm32f412zx.h:939
#define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0UL)
stm32f412zx.h:940
#define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8UL)
stm32f412zx.h:1046
#define DMA2 ((DMA_TypeDef *) DMA2_BASE)
stm32f413xx.h:1037
#define DMA2_Stream0_BASE (DMA2_BASE + 0x010UL)
stm32f413xx.h:1038
#define DMA2_Stream1_BASE (DMA2_BASE + 0x028UL)
stm32f413xx.h:1039
#define DMA2_Stream2_BASE (DMA2_BASE + 0x040UL)
stm32f413xx.h:1040
#define DMA2_Stream3_BASE (DMA2_BASE + 0x058UL)
stm32f413xx.h:1041
#define DMA2_Stream4_BASE (DMA2_BASE + 0x070UL)
stm32f413xx.h:1042
#define DMA2_Stream5_BASE (DMA2_BASE + 0x088UL)
stm32f413xx.h:1043
#define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0UL)
stm32f413xx.h:1044
#define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8UL)
stm32f413xx.h:1175
#define DMA2 ((DMA_TypeDef *) DMA2_BASE)
stm32f417xx.h:1071
#define DMA2_Stream0_BASE (DMA2_BASE + 0x010UL)
stm32f417xx.h:1076
#define DMA2_Stream5_BASE (DMA2_BASE + 0x088UL)
stm32f417xx.h:1077
#define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0UL)
stm32f417xx.h:1078
#define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8UL)
stm32f429xx.h:1136
#define DMA2_Stream0_BASE (DMA2_BASE + 0x010UL)
stm32f429xx.h:1137
#define DMA2_Stream1_BASE (DMA2_BASE + 0x028UL)
stm32f429xx.h:1138
#define DMA2_Stream2_BASE (DMA2_BASE + 0x040UL)
stm32f429xx.h:1139
#define DMA2_Stream3_BASE (DMA2_BASE + 0x058UL)
stm32f429xx.h:1140
#define DMA2_Stream4_BASE (DMA2_BASE + 0x070UL)
stm32f429xx.h:1141
#define DMA2_Stream5_BASE (DMA2_BASE + 0x088UL)
stm32f429xx.h:1142
#define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0UL)
stm32f429xx.h:1143
#define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8UL)
stm32f429xx.h:1271
#define DMA2 ((DMA_TypeDef *) DMA2_BASE)
stm32f439xx.h:1206
#define DMA2_Stream0_BASE (DMA2_BASE + 0x010UL)
stm32f439xx.h:1207
#define DMA2_Stream1_BASE (DMA2_BASE + 0x028UL)
stm32f439xx.h:1208
#define DMA2_Stream2_BASE (DMA2_BASE + 0x040UL)
stm32f439xx.h:1209
#define DMA2_Stream3_BASE (DMA2_BASE + 0x058UL)
stm32f439xx.h:1210
#define DMA2_Stream4_BASE (DMA2_BASE + 0x070UL)
stm32f439xx.h:1211
#define DMA2_Stream5_BASE (DMA2_BASE + 0x088UL)
stm32f439xx.h:1212
#define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0UL)
stm32f439xx.h:1213
#define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8UL)
stm32f439xx.h:1344
#define DMA2 ((DMA_TypeDef *) DMA2_BASE)
stm32f446xx.h:1020
#define DMA2_Stream0_BASE (DMA2_BASE + 0x010UL)
stm32f446xx.h:1021
#define DMA2_Stream1_BASE (DMA2_BASE + 0x028UL)
stm32f446xx.h:1022
#define DMA2_Stream2_BASE (DMA2_BASE + 0x040UL)
stm32f446xx.h:1023
#define DMA2_Stream3_BASE (DMA2_BASE + 0x058UL)
stm32f446xx.h:1024
#define DMA2_Stream4_BASE (DMA2_BASE + 0x070UL)
stm32f446xx.h:1025
#define DMA2_Stream5_BASE (DMA2_BASE + 0x088UL)
stm32f446xx.h:1026
#define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0UL)
stm32f446xx.h:1027
#define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8UL)
stm32f446xx.h:1141
#define DMA2 ((DMA_TypeDef *) DMA2_BASE)
stm32f469xx.h:1227
#define DMA2_Stream0_BASE (DMA2_BASE + 0x010UL)
stm32f469xx.h:1228
#define DMA2_Stream1_BASE (DMA2_BASE + 0x028UL)
stm32f469xx.h:1229
#define DMA2_Stream2_BASE (DMA2_BASE + 0x040UL)
stm32f469xx.h:1230
#define DMA2_Stream3_BASE (DMA2_BASE + 0x058UL)
stm32f469xx.h:1231
#define DMA2_Stream4_BASE (DMA2_BASE + 0x070UL)
stm32f469xx.h:1232
#define DMA2_Stream5_BASE (DMA2_BASE + 0x088UL)
stm32f469xx.h:1233
#define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0UL)
stm32f469xx.h:1234
#define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8UL)
stm32f469xx.h:1362
#define DMA2 ((DMA_TypeDef *) DMA2_BASE)
stm32f479xx.h:1297
#define DMA2_Stream0_BASE (DMA2_BASE + 0x010UL)
stm32f479xx.h:1302
#define DMA2_Stream5_BASE (DMA2_BASE + 0x088UL)
stm32f479xx.h:1303
#define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0UL)
stm32f479xx.h:1304
#define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8UL)