CMSIS + 0/1 examples
CodeScope will show references to DMA1_BASE from the following samples and libraries:
 
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CodeScopeSTM32 Libraries and SamplesCMSISDMA1_BASE

DMA1_BASE macro

Syntax

#define DMA1_BASE (AHB1PERIPH_BASE + 0x6000UL)

Examples

DMA1_BASE is referenced by 1 libraries and example projects.

References

LocationText
stm32f401xc.h:700
#define DMA1_BASE (AHB1PERIPH_BASE + 0x6000UL)
stm32f401xe.h:700
#define DMA1_BASE (AHB1PERIPH_BASE + 0x6000UL)
stm32f407xx.h:993
#define DMA1_BASE (AHB1PERIPH_BASE + 0x6000UL)
stm32f410rx.h:618
#define DMA1_BASE (AHB1PERIPH_BASE + 0x6000UL)
stm32f410tx.h:611
#define DMA1_BASE (AHB1PERIPH_BASE + 0x6000UL)
stm32f411xe.h:702
#define DMA1_BASE (AHB1PERIPH_BASE + 0x6000UL)
stm32f412zx.h:923
#define DMA1_BASE (AHB1PERIPH_BASE + 0x6000UL)
stm32f413xx.h:1027
#define DMA1_BASE (AHB1PERIPH_BASE + 0x6000UL)
stm32f417xx.h:1061
#define DMA1_BASE (AHB1PERIPH_BASE + 0x6000UL)
stm32f429xx.h:1126
#define DMA1_BASE (AHB1PERIPH_BASE + 0x6000UL)
stm32f439xx.h:1196
#define DMA1_BASE (AHB1PERIPH_BASE + 0x6000UL)
stm32f446xx.h:1010
#define DMA1_BASE (AHB1PERIPH_BASE + 0x6000UL)
stm32f469xx.h:1217
#define DMA1_BASE (AHB1PERIPH_BASE + 0x6000UL)
stm32f479xx.h:1287
#define DMA1_BASE (AHB1PERIPH_BASE + 0x6000UL)
stm32f401xc.h:701
#define DMA1_Stream0_BASE (DMA1_BASE + 0x010UL)
stm32f401xc.h:702
#define DMA1_Stream1_BASE (DMA1_BASE + 0x028UL)
stm32f401xc.h:703
#define DMA1_Stream2_BASE (DMA1_BASE + 0x040UL)
stm32f401xc.h:704
#define DMA1_Stream3_BASE (DMA1_BASE + 0x058UL)
stm32f401xc.h:705
#define DMA1_Stream4_BASE (DMA1_BASE + 0x070UL)
stm32f401xc.h:706
#define DMA1_Stream5_BASE (DMA1_BASE + 0x088UL)
stm32f401xc.h:707
#define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0UL)
stm32f401xc.h:708
#define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8UL)
stm32f401xc.h:788
#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
stm32f401xe.h:701
#define DMA1_Stream0_BASE (DMA1_BASE + 0x010UL)
stm32f401xe.h:702
#define DMA1_Stream1_BASE (DMA1_BASE + 0x028UL)
stm32f401xe.h:703
#define DMA1_Stream2_BASE (DMA1_BASE + 0x040UL)
stm32f401xe.h:704
#define DMA1_Stream3_BASE (DMA1_BASE + 0x058UL)
stm32f401xe.h:705
#define DMA1_Stream4_BASE (DMA1_BASE + 0x070UL)
stm32f401xe.h:706
#define DMA1_Stream5_BASE (DMA1_BASE + 0x088UL)
stm32f401xe.h:707
#define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0UL)
stm32f401xe.h:708
#define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8UL)
stm32f401xe.h:788
#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
stm32f407xx.h:994
#define DMA1_Stream0_BASE (DMA1_BASE + 0x010UL)
stm32f407xx.h:995
#define DMA1_Stream1_BASE (DMA1_BASE + 0x028UL)
stm32f407xx.h:996
#define DMA1_Stream2_BASE (DMA1_BASE + 0x040UL)
stm32f407xx.h:997
#define DMA1_Stream3_BASE (DMA1_BASE + 0x058UL)
stm32f407xx.h:998
#define DMA1_Stream4_BASE (DMA1_BASE + 0x070UL)
stm32f407xx.h:999
#define DMA1_Stream5_BASE (DMA1_BASE + 0x088UL)
stm32f407xx.h:1000
#define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0UL)
stm32f407xx.h:1001
#define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8UL)
stm32f407xx.h:1114
#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
stm32f410rx.h:619
#define DMA1_Stream0_BASE (DMA1_BASE + 0x010UL)
stm32f410rx.h:620
#define DMA1_Stream1_BASE (DMA1_BASE + 0x028UL)
stm32f410rx.h:621
#define DMA1_Stream2_BASE (DMA1_BASE + 0x040UL)
stm32f410rx.h:622
#define DMA1_Stream3_BASE (DMA1_BASE + 0x058UL)
stm32f410rx.h:623
#define DMA1_Stream4_BASE (DMA1_BASE + 0x070UL)
stm32f410rx.h:624
#define DMA1_Stream5_BASE (DMA1_BASE + 0x088UL)
stm32f410rx.h:625
#define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0UL)
stm32f410rx.h:626
#define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8UL)
stm32f410rx.h:686
#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
stm32f411xe.h:703
#define DMA1_Stream0_BASE (DMA1_BASE + 0x010UL)
stm32f411xe.h:704
#define DMA1_Stream1_BASE (DMA1_BASE + 0x028UL)
stm32f411xe.h:705
#define DMA1_Stream2_BASE (DMA1_BASE + 0x040UL)
stm32f411xe.h:706
#define DMA1_Stream3_BASE (DMA1_BASE + 0x058UL)
stm32f411xe.h:707
#define DMA1_Stream4_BASE (DMA1_BASE + 0x070UL)
stm32f411xe.h:708
#define DMA1_Stream5_BASE (DMA1_BASE + 0x088UL)
stm32f411xe.h:709
#define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0UL)
stm32f411xe.h:710
#define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8UL)
stm32f411xe.h:791
#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
stm32f412zx.h:924
#define DMA1_Stream0_BASE (DMA1_BASE + 0x010UL)
stm32f412zx.h:925
#define DMA1_Stream1_BASE (DMA1_BASE + 0x028UL)
stm32f412zx.h:926
#define DMA1_Stream2_BASE (DMA1_BASE + 0x040UL)
stm32f412zx.h:927
#define DMA1_Stream3_BASE (DMA1_BASE + 0x058UL)
stm32f412zx.h:928
#define DMA1_Stream4_BASE (DMA1_BASE + 0x070UL)
stm32f412zx.h:929
#define DMA1_Stream5_BASE (DMA1_BASE + 0x088UL)
stm32f412zx.h:930
#define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0UL)
stm32f412zx.h:931
#define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8UL)
stm32f412zx.h:1037
#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
stm32f413xx.h:1028
#define DMA1_Stream0_BASE (DMA1_BASE + 0x010UL)
stm32f413xx.h:1029
#define DMA1_Stream1_BASE (DMA1_BASE + 0x028UL)
stm32f413xx.h:1030
#define DMA1_Stream2_BASE (DMA1_BASE + 0x040UL)
stm32f413xx.h:1031
#define DMA1_Stream3_BASE (DMA1_BASE + 0x058UL)
stm32f413xx.h:1032
#define DMA1_Stream4_BASE (DMA1_BASE + 0x070UL)
stm32f413xx.h:1033
#define DMA1_Stream5_BASE (DMA1_BASE + 0x088UL)
stm32f413xx.h:1034
#define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0UL)
stm32f413xx.h:1035
#define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8UL)
stm32f413xx.h:1166
#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
stm32f429xx.h:1127
#define DMA1_Stream0_BASE (DMA1_BASE + 0x010UL)
stm32f429xx.h:1128
#define DMA1_Stream1_BASE (DMA1_BASE + 0x028UL)
stm32f429xx.h:1129
#define DMA1_Stream2_BASE (DMA1_BASE + 0x040UL)
stm32f429xx.h:1130
#define DMA1_Stream3_BASE (DMA1_BASE + 0x058UL)
stm32f429xx.h:1131
#define DMA1_Stream4_BASE (DMA1_BASE + 0x070UL)
stm32f429xx.h:1132
#define DMA1_Stream5_BASE (DMA1_BASE + 0x088UL)
stm32f429xx.h:1133
#define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0UL)
stm32f429xx.h:1134
#define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8UL)
stm32f429xx.h:1262
#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
stm32f439xx.h:1197
#define DMA1_Stream0_BASE (DMA1_BASE + 0x010UL)
stm32f439xx.h:1198
#define DMA1_Stream1_BASE (DMA1_BASE + 0x028UL)
stm32f439xx.h:1199
#define DMA1_Stream2_BASE (DMA1_BASE + 0x040UL)
stm32f439xx.h:1200
#define DMA1_Stream3_BASE (DMA1_BASE + 0x058UL)
stm32f439xx.h:1201
#define DMA1_Stream4_BASE (DMA1_BASE + 0x070UL)
stm32f439xx.h:1202
#define DMA1_Stream5_BASE (DMA1_BASE + 0x088UL)
stm32f439xx.h:1203
#define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0UL)
stm32f439xx.h:1204
#define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8UL)
stm32f439xx.h:1335
#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
stm32f446xx.h:1011
#define DMA1_Stream0_BASE (DMA1_BASE + 0x010UL)
stm32f446xx.h:1012
#define DMA1_Stream1_BASE (DMA1_BASE + 0x028UL)
stm32f446xx.h:1013
#define DMA1_Stream2_BASE (DMA1_BASE + 0x040UL)
stm32f446xx.h:1014
#define DMA1_Stream3_BASE (DMA1_BASE + 0x058UL)
stm32f446xx.h:1015
#define DMA1_Stream4_BASE (DMA1_BASE + 0x070UL)
stm32f446xx.h:1016
#define DMA1_Stream5_BASE (DMA1_BASE + 0x088UL)
stm32f446xx.h:1017
#define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0UL)
stm32f446xx.h:1018
#define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8UL)
stm32f446xx.h:1132
#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
stm32f469xx.h:1218
#define DMA1_Stream0_BASE (DMA1_BASE + 0x010UL)
stm32f469xx.h:1219
#define DMA1_Stream1_BASE (DMA1_BASE + 0x028UL)
stm32f469xx.h:1220
#define DMA1_Stream2_BASE (DMA1_BASE + 0x040UL)
stm32f469xx.h:1221
#define DMA1_Stream3_BASE (DMA1_BASE + 0x058UL)
stm32f469xx.h:1222
#define DMA1_Stream4_BASE (DMA1_BASE + 0x070UL)
stm32f469xx.h:1223
#define DMA1_Stream5_BASE (DMA1_BASE + 0x088UL)
stm32f469xx.h:1224
#define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0UL)
stm32f469xx.h:1225
#define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8UL)
stm32f469xx.h:1353
#define DMA1 ((DMA_TypeDef *) DMA1_BASE)