stm32l4_parts variable

static const struct stm32l4_part_info stm32l4_parts[] = { { .id = DEVID_STM32L47_L48XX, .revs = stm32l47_l48xx_revs, .num_revs = ARRAY_SIZE(stm32l47_l48xx_revs), .device_str = "STM32L47/L48xx", .max_flash_size_kb = 1024, .flags = F_HAS_DUAL_BANK, .flash_regs_base = 0x40022000, .fsize_addr = 0x1FFF75E0, .otp_base = 0x1FFF7000, .otp_size = 1024, }, { .id = DEVID_STM32L43_L44XX, .revs = stm32l43_l44xx_revs, .num_revs = ARRAY_SIZE(stm32l43_l44xx_revs), .device_str = "STM32L43/L44xx", .max_flash_size_kb = 256, .flags = F_NONE, .flash_regs_base = 0x40022000, .fsize_addr = 0x1FFF75E0, .otp_base = 0x1FFF7000, .otp_size = 1024, }, { .id = DEVID_STM32C01XX, .revs = stm32c01xx_revs, .num_revs = ARRAY_SIZE(stm32c01xx_revs), .device_str = "STM32C01xx", .max_flash_size_kb = 32, .flags = F_NONE, .flash_regs_base = 0x40022000, .fsize_addr = 0x1FFF75A0, .otp_base = 0x1FFF7000, .otp_size = 1024, }, { .id = DEVID_STM32C03XX, .revs = stm32c03xx_revs, .num_revs = ARRAY_SIZE(stm32c03xx_revs), .device_str = "STM32C03xx", .max_flash_size_kb = 32, .flags = F_NONE, .flash_regs_base = 0x40022000, .fsize_addr = 0x1FFF75A0, .otp_base = 0x1FFF7000, .otp_size = 1024, }, { .id = DEVID_STM32U53_U54XX, .revs = stm32u53_u54xx_revs, .num_revs = ARRAY_SIZE(stm32u53_u54xx_revs), .device_str = "STM32U535/U545", .max_flash_size_kb = 512, .flags = F_HAS_DUAL_BANK | F_QUAD_WORD_PROG | F_HAS_TZ | F_HAS_L5_FLASH_REGS, .flash_regs_base = 0x40022000, .fsize_addr = 0x0BFA07A0, .otp_base = 0x0BFA0000, .otp_size = 512, }, { .id = DEVID_STM32G05_G06XX, .revs = stm32g05_g06xx_revs, .num_revs = ARRAY_SIZE(stm32g05_g06xx_revs), .device_str = "STM32G05/G06xx", .max_flash_size_kb = 64, .flags = F_NONE, .flash_regs_base = 0x40022000, .fsize_addr = 0x1FFF75E0, .otp_base = 0x1FFF7000, .otp_size = 1024, }, { .id = DEVID_STM32G07_G08XX, .revs = stm32_g07_g08xx_revs, .num_revs = ARRAY_SIZE(stm32_g07_g08xx_revs), .device_str = "STM32G07/G08xx", .max_flash_size_kb = 128, .flags = F_NONE, .flash_regs_base = 0x40022000, .fsize_addr = 0x1FFF75E0, .otp_base = 0x1FFF7000, .otp_size = 1024, }, { .id = DEVID_STM32L49_L4AXX, .revs = stm32l49_l4axx_revs, .num_revs = ARRAY_SIZE(stm32l49_l4axx_revs), .device_str = "STM32L49/L4Axx", .max_flash_size_kb = 1024, .flags = F_HAS_DUAL_BANK, .flash_regs_base = 0x40022000, .fsize_addr = 0x1FFF75E0, .otp_base = 0x1FFF7000, .otp_size = 1024, }, { .id = DEVID_STM32L45_L46XX, .revs = stm32l45_l46xx_revs, .num_revs = ARRAY_SIZE(stm32l45_l46xx_revs), .device_str = "STM32L45/L46xx", .max_flash_size_kb = 512, .flags = F_NONE, .flash_regs_base = 0x40022000, .fsize_addr = 0x1FFF75E0, .otp_base = 0x1FFF7000, .otp_size = 1024, }, { .id = DEVID_STM32L41_L42XX, .revs = stm32l41_l42xx_revs, .num_revs = ARRAY_SIZE(stm32l41_l42xx_revs), .device_str = "STM32L41/L42xx", .max_flash_size_kb = 128, .flags = F_NONE, .flash_regs_base = 0x40022000, .fsize_addr = 0x1FFF75E0, .otp_base = 0x1FFF7000, .otp_size = 1024, }, { .id = DEVID_STM32G03_G04XX, .revs = stm32g03_g04xx_revs, .num_revs = ARRAY_SIZE(stm32g03_g04xx_revs), .device_str = "STM32G03x/G04xx", .max_flash_size_kb = 64, .flags = F_NONE, .flash_regs_base = 0x40022000, .fsize_addr = 0x1FFF75E0, .otp_base = 0x1FFF7000, .otp_size = 1024, }, { .id = DEVID_STM32G0B_G0CXX, .revs = stm32g0b_g0cxx_revs, .num_revs = ARRAY_SIZE(stm32g0b_g0cxx_revs), .device_str = "STM32G0B/G0Cx", .max_flash_size_kb = 512, .flags = F_HAS_DUAL_BANK, .flash_regs_base = 0x40022000, .fsize_addr = 0x1FFF75E0, .otp_base = 0x1FFF7000, .otp_size = 1024, }, { .id = DEVID_STM32G43_G44XX, .revs = stm32g43_g44xx_revs, .num_revs = ARRAY_SIZE(stm32g43_g44xx_revs), .device_str = "STM32G43/G44xx", .max_flash_size_kb = 128, .flags = F_NONE, .flash_regs_base = 0x40022000, .fsize_addr = 0x1FFF75E0, .otp_base = 0x1FFF7000, .otp_size = 1024, }, { .id = DEVID_STM32G47_G48XX, .revs = stm32g47_g48xx_revs, .num_revs = ARRAY_SIZE(stm32g47_g48xx_revs), .device_str = "STM32G47/G48xx", .max_flash_size_kb = 512, .flags = F_HAS_DUAL_BANK | F_USE_ALL_WRPXX, .flash_regs_base = 0x40022000, .fsize_addr = 0x1FFF75E0, .otp_base = 0x1FFF7000, .otp_size = 1024, }, { .id = DEVID_STM32L4R_L4SXX, .revs = stm32l4r_l4sxx_revs, .num_revs = ARRAY_SIZE(stm32l4r_l4sxx_revs), .device_str = "STM32L4R/L4Sxx", .max_flash_size_kb = 2048, .flags = F_HAS_DUAL_BANK | F_USE_ALL_WRPXX, .flash_regs_base = 0x40022000, .fsize_addr = 0x1FFF75E0, .otp_base = 0x1FFF7000, .otp_size = 1024, }, { .id = DEVID_STM32L4P_L4QXX, .revs = stm32l4p_l4qxx_revs, .num_revs = ARRAY_SIZE(stm32l4p_l4qxx_revs), .device_str = "STM32L4P/L4Qxx", .max_flash_size_kb = 1024, .flags = F_HAS_DUAL_BANK | F_USE_ALL_WRPXX, .flash_regs_base = 0x40022000, .fsize_addr = 0x1FFF75E0, .otp_base = 0x1FFF7000, .otp_size = 1024, }, { .id = DEVID_STM32L55_L56XX, .revs = stm32l55_l56xx_revs, .num_revs = ARRAY_SIZE(stm32l55_l56xx_revs), .device_str = "STM32L55/L56xx", .max_flash_size_kb = 512, .flags = F_HAS_DUAL_BANK | F_USE_ALL_WRPXX | F_HAS_TZ | F_HAS_L5_FLASH_REGS, .flash_regs_base = 0x40022000, .fsize_addr = 0x0BFA05E0, .otp_base = 0x0BFA0000, .otp_size = 512, }, { .id = DEVID_STM32G49_G4AXX, .revs = stm32g49_g4axx_revs, .num_revs = ARRAY_SIZE(stm32g49_g4axx_revs), .device_str = "STM32G49/G4Axx", .max_flash_size_kb = 512, .flags = F_NONE, .flash_regs_base = 0x40022000, .fsize_addr = 0x1FFF75E0, .otp_base = 0x1FFF7000, .otp_size = 1024, }, { .id = DEVID_STM32U59_U5AXX, .revs = stm32u59_u5axx_revs, .num_revs = ARRAY_SIZE(stm32u59_u5axx_revs), .device_str = "STM32U59/U5Axx", .max_flash_size_kb = 4096, .flags = F_HAS_DUAL_BANK | F_QUAD_WORD_PROG | F_HAS_TZ | F_HAS_L5_FLASH_REGS, .flash_regs_base = 0x40022000, .fsize_addr = 0x0BFA07A0, .otp_base = 0x0BFA0000, .otp_size = 512, }, { .id = DEVID_STM32U57_U58XX, .revs = stm32u57_u58xx_revs, .num_revs = ARRAY_SIZE(stm32u57_u58xx_revs), .device_str = "STM32U57/U58xx", .max_flash_size_kb = 2048, .flags = F_HAS_DUAL_BANK | F_QUAD_WORD_PROG | F_HAS_TZ | F_HAS_L5_FLASH_REGS, .flash_regs_base = 0x40022000, .fsize_addr = 0x0BFA07A0, .otp_base = 0x0BFA0000, .otp_size = 512, }, { .id = DEVID_STM32WBA5X, .revs = stm32wba5x_revs, .num_revs = ARRAY_SIZE(stm32wba5x_revs), .device_str = "STM32WBA5x", .max_flash_size_kb = 1024, .flags = F_QUAD_WORD_PROG | F_HAS_TZ | F_HAS_L5_FLASH_REGS, .flash_regs_base = 0x40022000, .fsize_addr = 0x0FF907A0, .otp_base = 0x0FF90000, .otp_size = 512, }, { .id = DEVID_STM32WB1XX, .revs = stm32wb1xx_revs, .num_revs = ARRAY_SIZE(stm32wb1xx_revs), .device_str = "STM32WB1x", .max_flash_size_kb = 320, .flags = F_NONE, .flash_regs_base = 0x58004000, .fsize_addr = 0x1FFF75E0, .otp_base = 0x1FFF7000, .otp_size = 1024, }, { .id = DEVID_STM32WB5XX, .revs = stm32wb5xx_revs, .num_revs = ARRAY_SIZE(stm32wb5xx_revs), .device_str = "STM32WB5x", .max_flash_size_kb = 1024, .flags = F_NONE, .flash_regs_base = 0x58004000, .fsize_addr = 0x1FFF75E0, .otp_base = 0x1FFF7000, .otp_size = 1024, }, { .id = DEVID_STM32WB3XX, .revs = stm32wb3xx_revs, .num_revs = ARRAY_SIZE(stm32wb3xx_revs), .device_str = "STM32WB3x", .max_flash_size_kb = 512, .flags = F_NONE, .flash_regs_base = 0x58004000, .fsize_addr = 0x1FFF75E0, .otp_base = 0x1FFF7000, .otp_size = 1024, }, { .id = DEVID_STM32WLE_WL5XX, .revs = stm32wle_wl5xx_revs, .num_revs = ARRAY_SIZE(stm32wle_wl5xx_revs), .device_str = "STM32WLE/WL5x", .max_flash_size_kb = 256, .flags = F_NONE, .flash_regs_base = 0x58004000, .fsize_addr = 0x1FFF75E0, .otp_base = 0x1FFF7000, .otp_size = 1024, }, };