OpenOCD
arm_instruction::::load_store is only used within OpenOCD.
 
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CodeScopeDevelopment ToolsOpenOCDarm_instruction::::load_store

arm_instruction::::load_store field

Syntax

struct arm_load_store_instr load_store;

References

LocationReferrerText
arm_disassembler.h:179
struct arm_load_store_instr load_store;
arm_disassembler.c:555evaluate_load_store()
instruction->info.load_store.rd = rd;
arm_disassembler.c:556evaluate_load_store()
instruction->info.load_store.rn = rn;
arm_disassembler.c:557evaluate_load_store()
instruction->info.load_store.u = u;
arm_disassembler.c:603evaluate_load_store()
instruction->info.load_store.offset_mode = 0;
arm_disassembler.c:604evaluate_load_store()
instruction->info.load_store.offset.offset = offset_12;
arm_disassembler.c:625evaluate_load_store()
instruction->info.load_store.offset_mode = 1;
arm_disassembler.c:626evaluate_load_store()
instruction->info.load_store.offset.reg.rm = rm;
arm_disassembler.c:627evaluate_load_store()
instruction->info.load_store.offset.reg.shift = shift;
arm_disassembler.c:628evaluate_load_store()
instruction->info.load_store.offset.reg.shift_imm = shift_imm;
arm_disassembler.c:667evaluate_load_store()
instruction->info.load_store.index_mode = 0;
arm_disassembler.c:681evaluate_load_store()
instruction->info.load_store.index_mode = 1;
arm_disassembler.c:696evaluate_load_store()
instruction->info.load_store.index_mode = 2;
arm_disassembler.c:1042evaluate_misc_load_store()
instruction->info.load_store.rd = rd;
arm_disassembler.c:1043evaluate_misc_load_store()
instruction->info.load_store.rn = rn;
arm_disassembler.c:1044evaluate_misc_load_store()
instruction->info.load_store.u = u;
arm_disassembler.c:1084evaluate_misc_load_store()
instruction->info.load_store.offset_mode = 0;
arm_disassembler.c:1085evaluate_misc_load_store()
instruction->info.load_store.offset.offset = offset_8;
arm_disassembler.c:1091evaluate_misc_load_store()
instruction->info.load_store.offset_mode = 1;
arm_disassembler.c:1092evaluate_misc_load_store()
instruction->info.load_store.offset.reg.rm = rm;
arm_disassembler.c:1093evaluate_misc_load_store()
instruction->info.load_store.offset.reg.shift = 0x0;
arm_disassembler.c:1094evaluate_misc_load_store()
instruction->info.load_store.offset.reg.shift_imm = 0x0;
arm_disassembler.c:1111evaluate_misc_load_store()
instruction->info.load_store.index_mode = 0;
arm_disassembler.c:1125evaluate_misc_load_store()
instruction->info.load_store.index_mode = 1;
arm_disassembler.c:1140evaluate_misc_load_store()
instruction->info.load_store.index_mode = 2;
arm_disassembler.c:2423evaluate_load_literal_thumb()
instruction->info.load_store.rd = rd;
arm_disassembler.c:2424evaluate_load_literal_thumb()
instruction->info.load_store.rn = 15 /*PC*/;
arm_disassembler.c:2425evaluate_load_literal_thumb()
instruction->info.load_store.index_mode = 0; /*offset*/
arm_disassembler.c:2426evaluate_load_literal_thumb()
instruction->info.load_store.offset_mode = 0; /*immediate*/
arm_disassembler.c:2427evaluate_load_literal_thumb()
instruction->info.load_store.offset.offset = immediate;
arm_disassembler.c:2486evaluate_load_store_reg_thumb()
instruction->info.load_store.rd = rd;
arm_disassembler.c:2487evaluate_load_store_reg_thumb()
instruction->info.load_store.rn = rn;
arm_disassembler.c:2488evaluate_load_store_reg_thumb()
instruction->info.load_store.index_mode = 0; /*offset*/
arm_disassembler.c:2489evaluate_load_store_reg_thumb()
instruction->info.load_store.offset_mode = 1; /*register*/
arm_disassembler.c:2490evaluate_load_store_reg_thumb()
instruction->info.load_store.offset.reg.rm = rm;
arm_disassembler.c:2527evaluate_load_store_imm_thumb()
instruction->info.load_store.rd = rd;
arm_disassembler.c:2528evaluate_load_store_imm_thumb()
instruction->info.load_store.rn = rn;
arm_disassembler.c:2529evaluate_load_store_imm_thumb()
instruction->info.load_store.index_mode = 0; /*offset*/
arm_disassembler.c:2530evaluate_load_store_imm_thumb()
instruction->info.load_store.offset_mode = 0; /*immediate*/
arm_disassembler.c:2531evaluate_load_store_imm_thumb()
instruction->info.load_store.offset.offset = offset << shift;
arm_disassembler.c:2556evaluate_load_store_stack_thumb()
instruction->info.load_store.rd = rd;
arm_disassembler.c:2557evaluate_load_store_stack_thumb()
instruction->info.load_store.rn = 13 /*SP*/;
arm_disassembler.c:2558evaluate_load_store_stack_thumb()
instruction->info.load_store.index_mode = 0; /*offset*/
arm_disassembler.c:2559evaluate_load_store_stack_thumb()
instruction->info.load_store.offset_mode = 0; /*immediate*/
arm_disassembler.c:2560evaluate_load_store_stack_thumb()
instruction->info.load_store.offset.offset = offset*4;
arm_simulator.c:421arm_simulate_step_core()
uint32_t rn = sim->get_reg_mode(sim, instruction.info.load_store.rn);
arm_simulator.c:424arm_simulate_step_core()
if (instruction.info.load_store.rn == 15)
arm_simulator.c:427arm_simulate_step_core()
if (instruction.info.load_store.offset_mode == 0) {
arm_simulator.c:428arm_simulate_step_core()
if (instruction.info.load_store.u)
arm_simulator.c:429arm_simulate_step_core()
modified_address = rn + instruction.info.load_store.offset.offset;
arm_simulator.c:431arm_simulate_step_core()
modified_address = rn - instruction.info.load_store.offset.offset;
arm_simulator.c:432arm_simulate_step_core()
} else if (instruction.info.load_store.offset_mode == 1) {
arm_simulator.c:435arm_simulate_step_core()
instruction.info.load_store.offset.reg.rm);
arm_simulator.c:436arm_simulate_step_core()
uint8_t shift = instruction.info.load_store.offset.reg.shift;
arm_simulator.c:437arm_simulate_step_core()
uint8_t shift_imm = instruction.info.load_store.offset.reg.shift_imm;
arm_simulator.c:442arm_simulate_step_core()
if (instruction.info.load_store.u)
arm_simulator.c:449arm_simulate_step_core()
if (instruction.info.load_store.index_mode == 0) {
arm_simulator.c:456arm_simulate_step_core()
} else if (instruction.info.load_store.index_mode == 1) {
arm_simulator.c:462arm_simulate_step_core()
} else if (instruction.info.load_store.index_mode == 2) {
arm_simulator.c:470arm_simulate_step_core()
if ((!dry_run_pc) || (instruction.info.load_store.rd == 15)) {
arm_simulator.c:477arm_simulate_step_core()
if (instruction.info.load_store.rd == 15)
arm_simulator.c:483arm_simulate_step_core()
if ((instruction.info.load_store.index_mode == 1) ||
arm_simulator.c:484arm_simulate_step_core()
(instruction.info.load_store.index_mode == 2))
arm_simulator.c:486arm_simulate_step_core()
instruction.info.load_store.rn,
arm_simulator.c:489arm_simulate_step_core()
if (instruction.info.load_store.rd == 15) {
arm_simulator.c:497arm_simulate_step_core()
sim->set_reg_mode(sim, instruction.info.load_store.rd, load_value);

Data Use

Type of arm_instruction::::load_store
arm_instruction::::load_store
all items filtered out