OpenOCD
arm_instruction::info is only used within OpenOCD.
 
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CodeScopeDevelopment ToolsOpenOCDarm_instruction::info

arm_instruction::info field

Syntax

union { struct arm_b_bl_bx_blx_instr b_bl_bx_blx; struct arm_data_proc_instr data_proc; struct arm_load_store_instr load_store; struct arm_load_store_multiple_instr load_store_multiple; } info;

References

LocationReferrerText
arm_disassembler.h:181
} info;
arm_disassembler.c:332evaluate_blx_imm()
instruction->info.b_bl_bx_blx.reg_operand = -1;
arm_disassembler.c:333evaluate_blx_imm()
instruction->info.b_bl_bx_blx.target_address = target_address;
arm_disassembler.c:374evaluate_b_bl()
instruction->info.b_bl_bx_blx.reg_operand = -1;
arm_disassembler.c:375evaluate_b_bl()
instruction->info.b_bl_bx_blx.target_address = target_address;
arm_disassembler.c:555evaluate_load_store()
instruction->info.load_store.rd = rd;
arm_disassembler.c:556evaluate_load_store()
instruction->info.load_store.rn = rn;
arm_disassembler.c:557evaluate_load_store()
instruction->info.load_store.u = u;
arm_disassembler.c:603evaluate_load_store()
instruction->info.load_store.offset_mode = 0;
arm_disassembler.c:604evaluate_load_store()
instruction->info.load_store.offset.offset = offset_12;
arm_disassembler.c:625evaluate_load_store()
instruction->info.load_store.offset_mode = 1;
arm_disassembler.c:626evaluate_load_store()
instruction->info.load_store.offset.reg.rm = rm;
arm_disassembler.c:627evaluate_load_store()
instruction->info.load_store.offset.reg.shift = shift;
arm_disassembler.c:628evaluate_load_store()
instruction->info.load_store.offset.reg.shift_imm = shift_imm;
arm_disassembler.c:667evaluate_load_store()
instruction->info.load_store.index_mode = 0;
arm_disassembler.c:681evaluate_load_store()
instruction->info.load_store.index_mode = 1;
arm_disassembler.c:696evaluate_load_store()
instruction->info.load_store.index_mode = 2;
arm_disassembler.c:1042evaluate_misc_load_store()
instruction->info.load_store.rd = rd;
arm_disassembler.c:1043evaluate_misc_load_store()
instruction->info.load_store.rn = rn;
arm_disassembler.c:1044evaluate_misc_load_store()
instruction->info.load_store.u = u;
arm_disassembler.c:1084evaluate_misc_load_store()
instruction->info.load_store.offset_mode = 0;
arm_disassembler.c:1085evaluate_misc_load_store()
instruction->info.load_store.offset.offset = offset_8;
arm_disassembler.c:1091evaluate_misc_load_store()
instruction->info.load_store.offset_mode = 1;
arm_disassembler.c:1092evaluate_misc_load_store()
instruction->info.load_store.offset.reg.rm = rm;
arm_disassembler.c:1093evaluate_misc_load_store()
instruction->info.load_store.offset.reg.shift = 0x0;
arm_disassembler.c:1094evaluate_misc_load_store()
instruction->info.load_store.offset.reg.shift_imm = 0x0;
arm_disassembler.c:1111evaluate_misc_load_store()
instruction->info.load_store.index_mode = 0;
arm_disassembler.c:1125evaluate_misc_load_store()
instruction->info.load_store.index_mode = 1;
arm_disassembler.c:1140evaluate_misc_load_store()
instruction->info.load_store.index_mode = 2;
arm_disassembler.c:1167evaluate_ldm_stm()
instruction->info.load_store_multiple.rn = rn;
arm_disassembler.c:1168evaluate_ldm_stm()
instruction->info.load_store_multiple.register_list = register_list;
arm_disassembler.c:1169evaluate_ldm_stm()
instruction->info.load_store_multiple.s = s;
arm_disassembler.c:1170evaluate_ldm_stm()
instruction->info.load_store_multiple.w = w;
arm_disassembler.c:1182evaluate_ldm_stm()
instruction->info.load_store_multiple.addressing_mode = 1;
arm_disassembler.c:1185evaluate_ldm_stm()
instruction->info.load_store_multiple.addressing_mode = 3;
arm_disassembler.c:1190evaluate_ldm_stm()
instruction->info.load_store_multiple.addressing_mode = 0;
arm_disassembler.c:1194evaluate_ldm_stm()
instruction->info.load_store_multiple.addressing_mode = 2;
arm_disassembler.c:1426evaluate_misc_instr()
instruction->info.b_bl_bx_blx.reg_operand = rm;
arm_disassembler.c:1427evaluate_misc_instr()
instruction->info.b_bl_bx_blx.target_address = -1;
arm_disassembler.c:1440evaluate_misc_instr()
instruction->info.b_bl_bx_blx.reg_operand = rm;
arm_disassembler.c:1441evaluate_misc_instr()
instruction->info.b_bl_bx_blx.target_address = -1;
arm_disassembler.c:1470evaluate_misc_instr()
instruction->info.b_bl_bx_blx.reg_operand = rm;
arm_disassembler.c:1471evaluate_misc_instr()
instruction->info.b_bl_bx_blx.target_address = -1;
arm_disassembler.c:1686evaluate_mov_imm()
instruction->info.data_proc.rd = rd;
arm_disassembler.c:1715evaluate_data_proc()
instruction->info.data_proc.rd = rd;
arm_disassembler.c:1716evaluate_data_proc()
instruction->info.data_proc.rn = rn;
arm_disassembler.c:1717evaluate_data_proc()
instruction->info.data_proc.s = s;
arm_disassembler.c:1795evaluate_data_proc()
instruction->info.data_proc.variant = 0;
arm_disassembler.c:1796evaluate_data_proc()
instruction->info.data_proc.shifter_operand.immediate.immediate = immediate;
arm_disassembler.c:1807evaluate_data_proc()
instruction->info.data_proc.variant = 1;
arm_disassembler.c:1808evaluate_data_proc()
instruction->info.data_proc.shifter_operand.immediate_shift.rm = rm;
arm_disassembler.c:1809evaluate_data_proc()
instruction->info.data_proc.shifter_operand.immediate_shift.shift_imm =
arm_disassembler.c:1811evaluate_data_proc()
instruction->info.data_proc.shifter_operand.immediate_shift.shift = shift;
arm_disassembler.c:1858evaluate_data_proc()
instruction->info.data_proc.variant = 2;
arm_disassembler.c:1859evaluate_data_proc()
instruction->info.data_proc.shifter_operand.register_shift.rm = rm;
arm_disassembler.c:1860evaluate_data_proc()
instruction->info.data_proc.shifter_operand.register_shift.rs = rs;
arm_disassembler.c:1861evaluate_data_proc()
instruction->info.data_proc.shifter_operand.register_shift.shift = shift;
arm_disassembler.c:2106evaluate_b_bl_blx_thumb()
instruction->info.b_bl_bx_blx.reg_operand = -1;
arm_disassembler.c:2107evaluate_b_bl_blx_thumb()
instruction->info.b_bl_bx_blx.target_address = target_address;
arm_disassembler.c:2131evaluate_add_sub_thumb()
instruction->info.data_proc.rd = rd;
arm_disassembler.c:2132evaluate_add_sub_thumb()
instruction->info.data_proc.rn = rn;
arm_disassembler.c:2133evaluate_add_sub_thumb()
instruction->info.data_proc.s = 1;
arm_disassembler.c:2136evaluate_add_sub_thumb()
instruction->info.data_proc.variant = 0;/*immediate*/
arm_disassembler.c:2137evaluate_add_sub_thumb()
instruction->info.data_proc.shifter_operand.immediate.immediate = rm_imm;
arm_disassembler.c:2142evaluate_add_sub_thumb()
instruction->info.data_proc.variant = 1;/*immediate shift*/
arm_disassembler.c:2143evaluate_add_sub_thumb()
instruction->info.data_proc.shifter_operand.immediate_shift.rm = rm_imm;
arm_disassembler.c:2165evaluate_shift_imm_thumb()
instruction->info.data_proc.shifter_operand.immediate_shift.shift = 0;
arm_disassembler.c:2170evaluate_shift_imm_thumb()
instruction->info.data_proc.shifter_operand.immediate_shift.shift = 1;
arm_disassembler.c:2175evaluate_shift_imm_thumb()
instruction->info.data_proc.shifter_operand.immediate_shift.shift = 2;
arm_disassembler.c:2182evaluate_shift_imm_thumb()
instruction->info.data_proc.rd = rd;
arm_disassembler.c:2183evaluate_shift_imm_thumb()
instruction->info.data_proc.rn = -1;
arm_disassembler.c:2184evaluate_shift_imm_thumb()
instruction->info.data_proc.s = 1;
arm_disassembler.c:2186evaluate_shift_imm_thumb()
instruction->info.data_proc.variant = 1;/*immediate_shift*/
arm_disassembler.c:2187evaluate_shift_imm_thumb()
instruction->info.data_proc.shifter_operand.immediate_shift.rm = rm;
arm_disassembler.c:2188evaluate_shift_imm_thumb()
instruction->info.data_proc.shifter_operand.immediate_shift.shift_imm = imm;
arm_disassembler.c:2205evaluate_data_proc_imm_thumb()
instruction->info.data_proc.rd = rd;
arm_disassembler.c:2206evaluate_data_proc_imm_thumb()
instruction->info.data_proc.rn = rd;
arm_disassembler.c:2207evaluate_data_proc_imm_thumb()
instruction->info.data_proc.s = 1;
arm_disassembler.c:2208evaluate_data_proc_imm_thumb()
instruction->info.data_proc.variant = 0;/*immediate*/
arm_disassembler.c:2209evaluate_data_proc_imm_thumb()
instruction->info.data_proc.shifter_operand.immediate.immediate = imm;
arm_disassembler.c:2215evaluate_data_proc_imm_thumb()
instruction->info.data_proc.rn = -1;
arm_disassembler.c:2220evaluate_data_proc_imm_thumb()
instruction->info.data_proc.rd = -1;
arm_disassembler.c:2254evaluate_data_proc_thumb()
instruction->info.data_proc.rd = rd;
arm_disassembler.c:2255evaluate_data_proc_thumb()
instruction->info.data_proc.rn = rd;
arm_disassembler.c:2256evaluate_data_proc_thumb()
instruction->info.data_proc.s = (!high_reg || (instruction->type == ARM_CMP));
arm_disassembler.c:2257evaluate_data_proc_thumb()
instruction->info.data_proc.variant = 1 /*immediate shift*/;
arm_disassembler.c:2258evaluate_data_proc_thumb()
instruction->info.data_proc.shifter_operand.immediate_shift.rm = rm;
arm_disassembler.c:2282evaluate_data_proc_thumb()
instruction->info.b_bl_bx_blx.reg_operand = rm;
arm_disassembler.c:2319evaluate_data_proc_thumb()
instruction->info.data_proc.variant = 2 /*register shift*/;
arm_disassembler.c:2320evaluate_data_proc_thumb()
instruction->info.data_proc.shifter_operand.register_shift.shift = 0;
arm_disassembler.c:2321evaluate_data_proc_thumb()
instruction->info.data_proc.shifter_operand.register_shift.rm = rd;
arm_disassembler.c:2322evaluate_data_proc_thumb()
instruction->info.data_proc.shifter_operand.register_shift.rs = rm;
arm_disassembler.c:2327evaluate_data_proc_thumb()
instruction->info.data_proc.variant = 2 /*register shift*/;
arm_disassembler.c:2328evaluate_data_proc_thumb()
instruction->info.data_proc.shifter_operand.register_shift.shift = 1;
arm_disassembler.c:2329evaluate_data_proc_thumb()
instruction->info.data_proc.shifter_operand.register_shift.rm = rd;
arm_disassembler.c:2330evaluate_data_proc_thumb()
instruction->info.data_proc.shifter_operand.register_shift.rs = rm;
arm_disassembler.c:2335evaluate_data_proc_thumb()
instruction->info.data_proc.variant = 2 /*register shift*/;
arm_disassembler.c:2336evaluate_data_proc_thumb()
instruction->info.data_proc.shifter_operand.register_shift.shift = 2;
arm_disassembler.c:2337evaluate_data_proc_thumb()
instruction->info.data_proc.shifter_operand.register_shift.rm = rd;
arm_disassembler.c:2338evaluate_data_proc_thumb()
instruction->info.data_proc.shifter_operand.register_shift.rs = rm;
arm_disassembler.c:2351evaluate_data_proc_thumb()
instruction->info.data_proc.variant = 2 /*register shift*/;
arm_disassembler.c:2352evaluate_data_proc_thumb()
instruction->info.data_proc.shifter_operand.register_shift.shift = 3;
arm_disassembler.c:2353evaluate_data_proc_thumb()
instruction->info.data_proc.shifter_operand.register_shift.rm = rd;
arm_disassembler.c:2354evaluate_data_proc_thumb()
instruction->info.data_proc.shifter_operand.register_shift.rs = rm;
arm_disassembler.c:2363evaluate_data_proc_thumb()
instruction->info.data_proc.variant = 0 /*immediate*/;
arm_disassembler.c:2364evaluate_data_proc_thumb()
instruction->info.data_proc.shifter_operand.immediate.immediate = 0;
arm_disassembler.c:2365evaluate_data_proc_thumb()
instruction->info.data_proc.rn = rm;
arm_disassembler.c:2423evaluate_load_literal_thumb()
instruction->info.load_store.rd = rd;
arm_disassembler.c:2424evaluate_load_literal_thumb()
instruction->info.load_store.rn = 15 /*PC*/;
arm_disassembler.c:2425evaluate_load_literal_thumb()
instruction->info.load_store.index_mode = 0; /*offset*/
arm_disassembler.c:2426evaluate_load_literal_thumb()
instruction->info.load_store.offset_mode = 0; /*immediate*/
arm_disassembler.c:2427evaluate_load_literal_thumb()
instruction->info.load_store.offset.offset = immediate;
arm_disassembler.c:2486evaluate_load_store_reg_thumb()
instruction->info.load_store.rd = rd;
arm_disassembler.c:2487evaluate_load_store_reg_thumb()
instruction->info.load_store.rn = rn;
arm_disassembler.c:2488evaluate_load_store_reg_thumb()
instruction->info.load_store.index_mode = 0; /*offset*/
arm_disassembler.c:2489evaluate_load_store_reg_thumb()
instruction->info.load_store.offset_mode = 1; /*register*/
arm_disassembler.c:2490evaluate_load_store_reg_thumb()
instruction->info.load_store.offset.reg.rm = rm;
arm_disassembler.c:2527evaluate_load_store_imm_thumb()
instruction->info.load_store.rd = rd;
arm_disassembler.c:2528evaluate_load_store_imm_thumb()
instruction->info.load_store.rn = rn;
arm_disassembler.c:2529evaluate_load_store_imm_thumb()
instruction->info.load_store.index_mode = 0; /*offset*/
arm_disassembler.c:2530evaluate_load_store_imm_thumb()
instruction->info.load_store.offset_mode = 0; /*immediate*/
arm_disassembler.c:2531evaluate_load_store_imm_thumb()
instruction->info.load_store.offset.offset = offset << shift;
arm_disassembler.c:2556evaluate_load_store_stack_thumb()
instruction->info.load_store.rd = rd;
arm_disassembler.c:2557evaluate_load_store_stack_thumb()
instruction->info.load_store.rn = 13 /*SP*/;
arm_disassembler.c:2558evaluate_load_store_stack_thumb()
instruction->info.load_store.index_mode = 0; /*offset*/
arm_disassembler.c:2559evaluate_load_store_stack_thumb()
instruction->info.load_store.offset_mode = 0; /*immediate*/
arm_disassembler.c:2560evaluate_load_store_stack_thumb()
instruction->info.load_store.offset.offset = offset*4;
arm_disassembler.c:2588evaluate_add_sp_pc_thumb()
instruction->info.data_proc.variant = 0 /* immediate */;
arm_disassembler.c:2589evaluate_add_sp_pc_thumb()
instruction->info.data_proc.rd = rd;
arm_disassembler.c:2590evaluate_add_sp_pc_thumb()
instruction->info.data_proc.rn = rn;
arm_disassembler.c:2591evaluate_add_sp_pc_thumb()
instruction->info.data_proc.shifter_operand.immediate.immediate = imm*4;
arm_disassembler.c:2616evaluate_adjust_stack_thumb()
instruction->info.data_proc.variant = 0 /* immediate */;
arm_disassembler.c:2617evaluate_adjust_stack_thumb()
instruction->info.data_proc.rd = 13 /*SP*/;
arm_disassembler.c:2618evaluate_adjust_stack_thumb()
instruction->info.data_proc.rn = 13 /*SP*/;
arm_disassembler.c:2619evaluate_adjust_stack_thumb()
instruction->info.data_proc.shifter_operand.immediate.immediate = imm*4;
arm_disassembler.c:2702evaluate_load_store_multiple_thumb()
instruction->info.load_store_multiple.register_list = reg_list;
arm_disassembler.c:2703evaluate_load_store_multiple_thumb()
instruction->info.load_store_multiple.rn = rn;
arm_disassembler.c:2704evaluate_load_store_multiple_thumb()
instruction->info.load_store_multiple.addressing_mode = addr_mode;
arm_disassembler.c:2742evaluate_cond_branch_thumb()
instruction->info.b_bl_bx_blx.reg_operand = -1;
arm_disassembler.c:2743evaluate_cond_branch_thumb()
instruction->info.b_bl_bx_blx.target_address = target_address;
arm_simulator.c:282arm_simulate_step_core()
uint32_t high = instruction.info.b_bl_bx_blx.target_address;
arm_simulator.c:289arm_simulate_step_core()
instruction.info.b_bl_bx_blx.target_address += high;
arm_simulator.c:299arm_simulate_step_core()
if (instruction.info.b_bl_bx_blx.reg_operand == -1)
arm_simulator.c:300arm_simulate_step_core()
target_address = instruction.info.b_bl_bx_blx.target_address;
arm_simulator.c:303arm_simulate_step_core()
instruction.info.b_bl_bx_blx.reg_operand);
arm_simulator.c:304arm_simulate_step_core()
if (instruction.info.b_bl_bx_blx.reg_operand == 15)
arm_simulator.c:350arm_simulate_step_core()
rn = sim->get_reg_mode(sim, instruction.info.data_proc.rn);
arm_simulator.c:355arm_simulate_step_core()
instruction.info.data_proc.variant,
arm_simulator.c:356arm_simulate_step_core()
instruction.info.data_proc.shifter_operand,
arm_simulator.c:360arm_simulate_step_core()
if (instruction.info.data_proc.rn == 15)
arm_simulator.c:391arm_simulate_step_core()
if (instruction.info.data_proc.rd == 15)
arm_simulator.c:398arm_simulate_step_core()
if (instruction.info.data_proc.rd == 15) {
arm_simulator.c:406arm_simulate_step_core()
sim->set_reg_mode(sim, instruction.info.data_proc.rd, rd);
arm_simulator.c:421arm_simulate_step_core()
uint32_t rn = sim->get_reg_mode(sim, instruction.info.load_store.rn);
arm_simulator.c:424arm_simulate_step_core()
if (instruction.info.load_store.rn == 15)
arm_simulator.c:427arm_simulate_step_core()
if (instruction.info.load_store.offset_mode == 0) {
arm_simulator.c:428arm_simulate_step_core()
if (instruction.info.load_store.u)
arm_simulator.c:429arm_simulate_step_core()
modified_address = rn + instruction.info.load_store.offset.offset;
arm_simulator.c:431arm_simulate_step_core()
modified_address = rn - instruction.info.load_store.offset.offset;
arm_simulator.c:432arm_simulate_step_core()
} else if (instruction.info.load_store.offset_mode == 1) {
arm_simulator.c:435arm_simulate_step_core()
instruction.info.load_store.offset.reg.rm);
arm_simulator.c:436arm_simulate_step_core()
uint8_t shift = instruction.info.load_store.offset.reg.shift;
arm_simulator.c:437arm_simulate_step_core()
uint8_t shift_imm = instruction.info.load_store.offset.reg.shift_imm;
arm_simulator.c:442arm_simulate_step_core()
if (instruction.info.load_store.u)
arm_simulator.c:449arm_simulate_step_core()
if (instruction.info.load_store.index_mode == 0) {
arm_simulator.c:456arm_simulate_step_core()
} else if (instruction.info.load_store.index_mode == 1) {
arm_simulator.c:462arm_simulate_step_core()
} else if (instruction.info.load_store.index_mode == 2) {
arm_simulator.c:470arm_simulate_step_core()
if ((!dry_run_pc) || (instruction.info.load_store.rd == 15)) {
arm_simulator.c:477arm_simulate_step_core()
if (instruction.info.load_store.rd == 15)
arm_simulator.c:483arm_simulate_step_core()
if ((instruction.info.load_store.index_mode == 1) ||
arm_simulator.c:484arm_simulate_step_core()
(instruction.info.load_store.index_mode == 2))
arm_simulator.c:486arm_simulate_step_core()
instruction.info.load_store.rn,
arm_simulator.c:489arm_simulate_step_core()
if (instruction.info.load_store.rd == 15) {
arm_simulator.c:497arm_simulate_step_core()
sim->set_reg_mode(sim, instruction.info.load_store.rd, load_value);
arm_simulator.c:503arm_simulate_step_core()
uint32_t rn = sim->get_reg_mode(sim, instruction.info.load_store_multiple.rn);
arm_simulator.c:508arm_simulate_step_core()
if (instruction.info.load_store_multiple.register_list & (1 << i))
arm_simulator.c:512arm_simulate_step_core()
switch (instruction.info.load_store_multiple.addressing_mode) {
arm_simulator.c:528arm_simulate_step_core()
if (instruction.info.load_store_multiple.register_list & (1 << i)) {
arm_simulator.c:536arm_simulate_step_core()
if (instruction.info.load_store_multiple.register_list & 0x8000) {
arm_simulator.c:543arm_simulate_step_core()
if (instruction.info.load_store_multiple.s) {
arm_simulator.c:544arm_simulate_step_core()
if (instruction.info.load_store_multiple.register_list & 0x8000)
arm_simulator.c:549arm_simulate_step_core()
if (instruction.info.load_store_multiple.register_list & (1 << i)) {
arm_simulator.c:568arm_simulate_step_core()
if (instruction.info.load_store_multiple.w)
arm_simulator.c:569arm_simulate_step_core()
sim->set_reg_mode(sim, instruction.info.load_store_multiple.rn, rn);
arm_simulator.c:572arm_simulate_step_core()
if (instruction.info.load_store_multiple.register_list & 0x8000)
arm_simulator.c:584arm_simulate_step_core()
instruction.info.load_store_multiple.rn);
arm_simulator.c:588arm_simulate_step_core()
if (instruction.info.load_store_multiple.register_list & (1 << i))
arm_simulator.c:592arm_simulate_step_core()
switch (instruction.info.load_store_multiple.addressing_mode) {
arm_simulator.c:608arm_simulate_step_core()
if (instruction.info.load_store_multiple.register_list & (1 << i)) {
arm_simulator.c:615arm_simulate_step_core()
if (instruction.info.load_store_multiple.w)
arm_simulator.c:617arm_simulate_step_core()
instruction.info.load_store_multiple.rn, rn);
etm.c:1057etmv1_analyze_trace()
if (instruction.info.load_store_multiple.register_list
etm.c:1089etmv1_analyze_trace()
(instruction.info.b_bl_bx_blx.target_address != 0xffffffff))
etm.c:1090etmv1_analyze_trace()
next_pc = instruction.info.b_bl_bx_blx.target_address;
xscale.c:2791xscale_analyze_trace()
current_pc = instruction.info.b_bl_bx_blx.target_address;

Data Use

Type of arm_instruction::info
arm_instruction::info
arm_instruction::
all items filtered out