MIPS64_NUM_CORE_REGS - syntax, references, description

References

Location	Text
mips64.h:65	#define MIPS64_NUM_CORE_REGS 34
mips64.c:65	{ MIPS64_NUM_CORE_REGS + 0, "pc", REG_TYPE_UINT64, NULL,
mips64.c:67	{ MIPS64_NUM_CORE_REGS + 1, "Random", REG_TYPE_UINT32, NULL,
mips64.c:69	{ MIPS64_NUM_CORE_REGS + 2, "Entrylo_0", REG_TYPE_UINT64, NULL,
mips64.c:71	{ MIPS64_NUM_CORE_REGS + 3, "Entrylo_1", REG_TYPE_UINT64, NULL,
mips64.c:73	{ MIPS64_NUM_CORE_REGS + 4, "Context", REG_TYPE_UINT64, NULL,
mips64.c:75	{ MIPS64_NUM_CORE_REGS + 5, "Pagemask", REG_TYPE_UINT32, NULL,
mips64.c:77	{ MIPS64_NUM_CORE_REGS + 6, "Wired", REG_TYPE_UINT32, NULL,
mips64.c:79	{ MIPS64_NUM_CORE_REGS + 7, "badvaddr", REG_TYPE_UINT64, NULL,
mips64.c:81	{ MIPS64_NUM_CORE_REGS + 8, "Count", REG_TYPE_UINT32, NULL,
mips64.c:83	{ MIPS64_NUM_CORE_REGS + 9, "EntryHi", REG_TYPE_UINT64, NULL,
mips64.c:85	{ MIPS64_NUM_CORE_REGS + 10, "Compare", REG_TYPE_UINT32, NULL,
mips64.c:87	{ MIPS64_NUM_CORE_REGS + 11, "status", REG_TYPE_UINT32, NULL,
mips64.c:89	{ MIPS64_NUM_CORE_REGS + 12, "cause", REG_TYPE_UINT32, NULL,
mips64.c:91	{ MIPS64_NUM_CORE_REGS + 13, "EPC", REG_TYPE_UINT64, NULL,
mips64.c:93	{ MIPS64_NUM_CORE_REGS + 14, "PrID", REG_TYPE_UINT32, NULL,
mips64.c:95	{ MIPS64_NUM_CORE_REGS + 15, "Config", REG_TYPE_UINT32, NULL,
mips64.c:97	{ MIPS64_NUM_CORE_REGS + 16, "LLA", REG_TYPE_UINT32, NULL,
mips64.c:99	{ MIPS64_NUM_CORE_REGS + 17, "WatchLo0", REG_TYPE_UINT64, NULL,
mips64.c:101	{ MIPS64_NUM_CORE_REGS + 18, "WatchLo1", REG_TYPE_UINT64, NULL,
mips64.c:103	{ MIPS64_NUM_CORE_REGS + 19, "WatchHi0", REG_TYPE_UINT32, NULL,
mips64.c:105	{ MIPS64_NUM_CORE_REGS + 20, "WatchHi1", REG_TYPE_UINT32, NULL,
mips64.c:107	{ MIPS64_NUM_CORE_REGS + 21, "Xcontext", REG_TYPE_UINT64, NULL,
mips64.c:109	{ MIPS64_NUM_CORE_REGS + 22, "ChipMemCtrl", REG_TYPE_UINT32, NULL,
mips64.c:111	{ MIPS64_NUM_CORE_REGS + 23, "Debug", REG_TYPE_UINT32, NULL,
mips64.c:113	{ MIPS64_NUM_CORE_REGS + 24, "Perfcount, sel=0", REG_TYPE_UINT32, NULL,
mips64.c:115	{ MIPS64_NUM_CORE_REGS + 25, "Perfcount, sel=1", REG_TYPE_UINT64, NULL,
mips64.c:117	{ MIPS64_NUM_CORE_REGS + 26, "Perfcount, sel=2", REG_TYPE_UINT32, NULL,
mips64.c:119	{ MIPS64_NUM_CORE_REGS + 27, "Perfcount, sel=3", REG_TYPE_UINT64, NULL,
mips64.c:121	{ MIPS64_NUM_CORE_REGS + 28, "ECC", REG_TYPE_UINT32, NULL,
mips64.c:123	{ MIPS64_NUM_CORE_REGS + 29, "CacheErr", REG_TYPE_UINT32, NULL,
mips64.c:125	{ MIPS64_NUM_CORE_REGS + 30, "TagLo", REG_TYPE_UINT32, NULL,
mips64.c:127	{ MIPS64_NUM_CORE_REGS + 31, "TagHi", REG_TYPE_UINT32, NULL,
mips64.c:129	{ MIPS64_NUM_CORE_REGS + 32, "DataHi", REG_TYPE_UINT64, NULL,
mips64.c:131	{ MIPS64_NUM_CORE_REGS + 33, "EEPC", REG_TYPE_UINT64, NULL,
mips64.h:69	#define MIPS64_NUM_REGS (MIPS64_NUM_CORE_REGS + \
mips64.h:73	#define MIPS64_NUM_CORE_C0_REGS (MIPS64_NUM_CORE_REGS + MIPS64_NUM_C0_REGS)
mips64.h:75	#define MIPS64_PC MIPS64_NUM_CORE_REGS
mips64_pracc.c:880	MIPS64_LD(2, MIPS64_NUM_CORE_REGS * 8, 1),
mips64_pracc.c:882	MIPS64_LD(2, (MIPS64_NUM_CORE_REGS + 2) * 8, 1),
mips64_pracc.c:884	MIPS64_LD(2, (MIPS64_NUM_CORE_REGS + 3) * 8, 1),
mips64_pracc.c:886	MIPS64_LD(2, (MIPS64_NUM_CORE_REGS + 4) * 8, 1),
mips64_pracc.c:888	MIPS64_LD(2, (MIPS64_NUM_CORE_REGS + 5) * 8, 1),
mips64_pracc.c:890	MIPS64_LD(2, (MIPS64_NUM_CORE_REGS + 6) * 8, 1),
mips64_pracc.c:892	MIPS64_LD(2, (MIPS64_NUM_CORE_REGS + 8) * 8, 1),
mips64_pracc.c:894	MIPS64_LD(2, (MIPS64_NUM_CORE_REGS + 9) * 8, 1),
mips64_pracc.c:896	MIPS64_LD(2, (MIPS64_NUM_CORE_REGS + 10) * 8, 1),
mips64_pracc.c:898	MIPS64_LD(2, (MIPS64_NUM_CORE_REGS + 11) * 8, 1),
mips64_pracc.c:900	MIPS64_LD(2, (MIPS64_NUM_CORE_REGS + 12) * 8, 1),
mips64_pracc.c:902	MIPS64_LD(2, (MIPS64_NUM_CORE_REGS + 13) * 8, 1),
mips64_pracc.c:904	MIPS64_LD(2, (MIPS64_NUM_CORE_REGS + 15) * 8, 1),
mips64_pracc.c:906	MIPS64_LD(2, (MIPS64_NUM_CORE_REGS + 16) * 8, 1),
mips64_pracc.c:908	MIPS64_LD(2, (MIPS64_NUM_CORE_REGS + 21) * 8, 1),
mips64_pracc.c:910	MIPS64_LD(2, (MIPS64_NUM_CORE_REGS + 22) * 8, 1),
mips64_pracc.c:912	MIPS64_LD(2, (MIPS64_NUM_CORE_REGS + 24) * 8, 1),
mips64_pracc.c:914	MIPS64_LD(2, (MIPS64_NUM_CORE_REGS + 25) * 8, 1),
mips64_pracc.c:916	MIPS64_LD(2, (MIPS64_NUM_CORE_REGS + 26) * 8, 1),
mips64_pracc.c:918	MIPS64_LD(2, (MIPS64_NUM_CORE_REGS + 27) * 8, 1),
mips64_pracc.c:920	MIPS64_LD(2, (MIPS64_NUM_CORE_REGS + 28) * 8, 1),
mips64_pracc.c:922	MIPS64_LD(2, (MIPS64_NUM_CORE_REGS + 29) * 8, 1),
mips64_pracc.c:924	MIPS64_LD(2, (MIPS64_NUM_CORE_REGS + 30) * 8, 1),
mips64_pracc.c:926	MIPS64_LD(2, (MIPS64_NUM_CORE_REGS + 31) * 8, 1),
mips64_pracc.c:928	MIPS64_LD(2, (MIPS64_NUM_CORE_REGS + 32) * 8, 1),
mips64_pracc.c:930	MIPS64_LD(2, (MIPS64_NUM_CORE_REGS + 33) * 8, 1),
mips64_pracc.c:1099	MIPS64_SD(2, MIPS64_NUM_CORE_REGS * 8, 1),
mips64_pracc.c:1101	MIPS64_SD(2, (MIPS64_NUM_CORE_REGS + 1) * 8, 1),
mips64_pracc.c:1103	MIPS64_SD(2, (MIPS64_NUM_CORE_REGS + 2) * 8, 1),
mips64_pracc.c:1105	MIPS64_SD(2, (MIPS64_NUM_CORE_REGS + 3) * 8, 1),
mips64_pracc.c:1107	MIPS64_SD(2, (MIPS64_NUM_CORE_REGS + 4) * 8, 1),
mips64_pracc.c:1109	MIPS64_SD(2, (MIPS64_NUM_CORE_REGS + 5) * 8, 1),
mips64_pracc.c:1111	MIPS64_SD(2, (MIPS64_NUM_CORE_REGS + 6) * 8, 1),
mips64_pracc.c:1113	MIPS64_SD(2, (MIPS64_NUM_CORE_REGS + 7) * 8, 1),
mips64_pracc.c:1115	MIPS64_SD(2, (MIPS64_NUM_CORE_REGS + 8) * 8, 1),
mips64_pracc.c:1117	MIPS64_SD(2, (MIPS64_NUM_CORE_REGS + 9) * 8, 1),
mips64_pracc.c:1119	MIPS64_SD(2, (MIPS64_NUM_CORE_REGS + 10) * 8, 1),
mips64_pracc.c:1121	MIPS64_SD(2, (MIPS64_NUM_CORE_REGS + 11) * 8, 1),
mips64_pracc.c:1123	MIPS64_SD(2, (MIPS64_NUM_CORE_REGS + 12) * 8, 1),
mips64_pracc.c:1125	MIPS64_SD(2, (MIPS64_NUM_CORE_REGS + 13) * 8, 1),
mips64_pracc.c:1127	MIPS64_SD(2, (MIPS64_NUM_CORE_REGS + 14) * 8, 1),
mips64_pracc.c:1129	MIPS64_SD(2, (MIPS64_NUM_CORE_REGS + 15) * 8, 1),
mips64_pracc.c:1131	MIPS64_SD(2, (MIPS64_NUM_CORE_REGS + 16) * 8, 1),
mips64_pracc.c:1133	MIPS64_SD(2, (MIPS64_NUM_CORE_REGS + 21) * 8, 1),
mips64_pracc.c:1135	MIPS64_SD(2, (MIPS64_NUM_CORE_REGS + 22) * 8, 1),
mips64_pracc.c:1137	MIPS64_SD(2, (MIPS64_NUM_CORE_REGS + 23) * 8, 1),
mips64_pracc.c:1139	MIPS64_SD(2, (MIPS64_NUM_CORE_REGS + 24) * 8, 1),
mips64_pracc.c:1141	MIPS64_SD(2, (MIPS64_NUM_CORE_REGS + 25) * 8, 1),
mips64_pracc.c:1143	MIPS64_SD(2, (MIPS64_NUM_CORE_REGS + 26) * 8, 1),
mips64_pracc.c:1145	MIPS64_SD(2, (MIPS64_NUM_CORE_REGS + 27) * 8, 1),
mips64_pracc.c:1147	MIPS64_SD(2, (MIPS64_NUM_CORE_REGS + 28) * 8, 1),
mips64_pracc.c:1149	MIPS64_SD(2, (MIPS64_NUM_CORE_REGS + 29) * 8, 1),
mips64_pracc.c:1151	MIPS64_SD(2, (MIPS64_NUM_CORE_REGS + 30) * 8, 1),
mips64_pracc.c:1153	MIPS64_SD(2, (MIPS64_NUM_CORE_REGS + 31) * 8, 1),
mips64_pracc.c:1155	MIPS64_SD(2, (MIPS64_NUM_CORE_REGS + 32) * 8, 1),
mips64_pracc.c:1157	MIPS64_SD(2, (MIPS64_NUM_CORE_REGS + 33) * 8, 1),

MIPS64_NUM_CORE_REGS macro

Syntax

References