OpenOCD
MIPS64_NUM_CORE_C0_REGS is only used within OpenOCD.
 
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CodeScopeDevelopment ToolsOpenOCDMIPS64_NUM_CORE_C0_REGS

MIPS64_NUM_CORE_C0_REGS macro

Syntax

#define MIPS64_NUM_CORE_C0_REGS (MIPS64_NUM_CORE_REGS + MIPS64_NUM_C0_REGS)

References

LocationText
mips64.h:73
#define MIPS64_NUM_CORE_C0_REGS (MIPS64_NUM_CORE_REGS + MIPS64_NUM_C0_REGS)
mips64.c:133
{ MIPS64_NUM_CORE_C0_REGS + 0, "f0", REG_TYPE_IEEE_DOUBLE, NULL,
mips64.c:135
{ MIPS64_NUM_CORE_C0_REGS + 1, "f1", REG_TYPE_IEEE_DOUBLE, NULL,
mips64.c:137
{ MIPS64_NUM_CORE_C0_REGS + 2, "f2", REG_TYPE_IEEE_DOUBLE, NULL,
mips64.c:139
{ MIPS64_NUM_CORE_C0_REGS + 3, "f3", REG_TYPE_IEEE_DOUBLE, NULL,
mips64.c:141
{ MIPS64_NUM_CORE_C0_REGS + 4, "f4", REG_TYPE_IEEE_DOUBLE, NULL,
mips64.c:143
{ MIPS64_NUM_CORE_C0_REGS + 5, "f5", REG_TYPE_IEEE_DOUBLE, NULL,
mips64.c:145
{ MIPS64_NUM_CORE_C0_REGS + 6, "f6", REG_TYPE_IEEE_DOUBLE, NULL,
mips64.c:147
{ MIPS64_NUM_CORE_C0_REGS + 7, "f7", REG_TYPE_IEEE_DOUBLE, NULL,
mips64.c:149
{ MIPS64_NUM_CORE_C0_REGS + 8, "f8", REG_TYPE_IEEE_DOUBLE, NULL,
mips64.c:151
{ MIPS64_NUM_CORE_C0_REGS + 9, "f9", REG_TYPE_IEEE_DOUBLE, NULL,
mips64.c:153
{ MIPS64_NUM_CORE_C0_REGS + 10, "f10", REG_TYPE_IEEE_DOUBLE, NULL,
mips64.c:155
{ MIPS64_NUM_CORE_C0_REGS + 11, "f11", REG_TYPE_IEEE_DOUBLE, NULL,
mips64.c:157
{ MIPS64_NUM_CORE_C0_REGS + 12, "f12", REG_TYPE_IEEE_DOUBLE, NULL,
mips64.c:159
{ MIPS64_NUM_CORE_C0_REGS + 13, "f13", REG_TYPE_IEEE_DOUBLE, NULL,
mips64.c:161
{ MIPS64_NUM_CORE_C0_REGS + 14, "f14", REG_TYPE_IEEE_DOUBLE, NULL,
mips64.c:163
{ MIPS64_NUM_CORE_C0_REGS + 15, "f15", REG_TYPE_IEEE_DOUBLE, NULL,
mips64.c:165
{ MIPS64_NUM_CORE_C0_REGS + 16, "f16", REG_TYPE_IEEE_DOUBLE, NULL,
mips64.c:167
{ MIPS64_NUM_CORE_C0_REGS + 17, "f17", REG_TYPE_IEEE_DOUBLE, NULL,
mips64.c:169
{ MIPS64_NUM_CORE_C0_REGS + 18, "f18", REG_TYPE_IEEE_DOUBLE, NULL,
mips64.c:171
{ MIPS64_NUM_CORE_C0_REGS + 19, "f19", REG_TYPE_IEEE_DOUBLE, NULL,
mips64.c:173
{ MIPS64_NUM_CORE_C0_REGS + 20, "f20", REG_TYPE_IEEE_DOUBLE, NULL,
mips64.c:175
{ MIPS64_NUM_CORE_C0_REGS + 21, "f21", REG_TYPE_IEEE_DOUBLE, NULL,
mips64.c:177
{ MIPS64_NUM_CORE_C0_REGS + 22, "f22", REG_TYPE_IEEE_DOUBLE, NULL,
mips64.c:179
{ MIPS64_NUM_CORE_C0_REGS + 23, "f23", REG_TYPE_IEEE_DOUBLE, NULL,
mips64.c:181
{ MIPS64_NUM_CORE_C0_REGS + 24, "f24", REG_TYPE_IEEE_DOUBLE, NULL,
mips64.c:183
{ MIPS64_NUM_CORE_C0_REGS + 25, "f25", REG_TYPE_IEEE_DOUBLE, NULL,
mips64.c:185
{ MIPS64_NUM_CORE_C0_REGS + 26, "f26", REG_TYPE_IEEE_DOUBLE, NULL,
mips64.c:187
{ MIPS64_NUM_CORE_C0_REGS + 27, "f27", REG_TYPE_IEEE_DOUBLE, NULL,
mips64.c:189
{ MIPS64_NUM_CORE_C0_REGS + 28, "f28", REG_TYPE_IEEE_DOUBLE, NULL,
mips64.c:191
{ MIPS64_NUM_CORE_C0_REGS + 29, "f29", REG_TYPE_IEEE_DOUBLE, NULL,
mips64.c:193
{ MIPS64_NUM_CORE_C0_REGS + 30, "f30", REG_TYPE_IEEE_DOUBLE, NULL,
mips64.c:195
{ MIPS64_NUM_CORE_C0_REGS + 31, "f31", REG_TYPE_IEEE_DOUBLE, NULL,
mips64.c:197
{ MIPS64_NUM_CORE_C0_REGS + 32, "fcsr", REG_TYPE_INT, "float",
mips64.c:199
{ MIPS64_NUM_CORE_C0_REGS + 33, "fir", REG_TYPE_INT, "float",
mips64.c:201
{ MIPS64_NUM_CORE_C0_REGS + 34, "fconfig", REG_TYPE_INT, "float",
mips64.c:203
{ MIPS64_NUM_CORE_C0_REGS + 35, "fccr", REG_TYPE_INT, "float",
mips64.c:205
{ MIPS64_NUM_CORE_C0_REGS + 36, "fexr", REG_TYPE_INT, "float",
mips64.c:207
{ MIPS64_NUM_CORE_C0_REGS + 37, "fenr", REG_TYPE_INT, "float",
mips64_pracc.c:939
MIPS64_LD(2, (MIPS64_NUM_CORE_C0_REGS + 33) * 8, 1),
mips64_pracc.c:941
MIPS64_LD(2, (MIPS64_NUM_CORE_C0_REGS + 32) * 8, 1),
mips64_pracc.c:943
MIPS64_LD(2, (MIPS64_NUM_CORE_C0_REGS + 34) * 8, 1),
mips64_pracc.c:945
MIPS64_LD(2, (MIPS64_NUM_CORE_C0_REGS + 35) * 8, 1),
mips64_pracc.c:947
MIPS64_LD(2, (MIPS64_NUM_CORE_C0_REGS + 36) * 8, 1),
mips64_pracc.c:949
MIPS64_LD(2, (MIPS64_NUM_CORE_C0_REGS + 37) * 8, 1),
mips64_pracc.c:951
MIPS64_LD(2, (MIPS64_NUM_CORE_C0_REGS + 0) * 8, 1),
mips64_pracc.c:953
MIPS64_LD(2, (MIPS64_NUM_CORE_C0_REGS + 1) * 8, 1),
mips64_pracc.c:955
MIPS64_LD(2, (MIPS64_NUM_CORE_C0_REGS + 2) * 8, 1),
mips64_pracc.c:957
MIPS64_LD(2, (MIPS64_NUM_CORE_C0_REGS + 3) * 8, 1),
mips64_pracc.c:959
MIPS64_LD(2, (MIPS64_NUM_CORE_C0_REGS + 4) * 8, 1),
mips64_pracc.c:961
MIPS64_LD(2, (MIPS64_NUM_CORE_C0_REGS + 5) * 8, 1),
mips64_pracc.c:963
MIPS64_LD(2, (MIPS64_NUM_CORE_C0_REGS + 6) * 8, 1),
mips64_pracc.c:965
MIPS64_LD(2, (MIPS64_NUM_CORE_C0_REGS + 7) * 8, 1),
mips64_pracc.c:967
MIPS64_LD(2, (MIPS64_NUM_CORE_C0_REGS + 8) * 8, 1),
mips64_pracc.c:969
MIPS64_LD(2, (MIPS64_NUM_CORE_C0_REGS + 9) * 8, 1),
mips64_pracc.c:971
MIPS64_LD(2, (MIPS64_NUM_CORE_C0_REGS + 10) * 8, 1),
mips64_pracc.c:973
MIPS64_LD(2, (MIPS64_NUM_CORE_C0_REGS + 11) * 8, 1),
mips64_pracc.c:975
MIPS64_LD(2, (MIPS64_NUM_CORE_C0_REGS + 12) * 8, 1),
mips64_pracc.c:977
MIPS64_LD(2, (MIPS64_NUM_CORE_C0_REGS + 13) * 8, 1),
mips64_pracc.c:979
MIPS64_LD(2, (MIPS64_NUM_CORE_C0_REGS + 14) * 8, 1),
mips64_pracc.c:981
MIPS64_LD(2, (MIPS64_NUM_CORE_C0_REGS + 15) * 8, 1),
mips64_pracc.c:983
MIPS64_LD(2, (MIPS64_NUM_CORE_C0_REGS + 16) * 8, 1),
mips64_pracc.c:985
MIPS64_LD(2, (MIPS64_NUM_CORE_C0_REGS + 17) * 8, 1),
mips64_pracc.c:987
MIPS64_LD(2, (MIPS64_NUM_CORE_C0_REGS + 18) * 8, 1),
mips64_pracc.c:989
MIPS64_LD(2, (MIPS64_NUM_CORE_C0_REGS + 19) * 8, 1),
mips64_pracc.c:991
MIPS64_LD(2, (MIPS64_NUM_CORE_C0_REGS + 20) * 8, 1),
mips64_pracc.c:993
MIPS64_LD(2, (MIPS64_NUM_CORE_C0_REGS + 21) * 8, 1),
mips64_pracc.c:995
MIPS64_LD(2, (MIPS64_NUM_CORE_C0_REGS + 22) * 8, 1),
mips64_pracc.c:997
MIPS64_LD(2, (MIPS64_NUM_CORE_C0_REGS + 23) * 8, 1),
mips64_pracc.c:999
MIPS64_LD(2, (MIPS64_NUM_CORE_C0_REGS + 24) * 8, 1),
mips64_pracc.c:1001
MIPS64_LD(2, (MIPS64_NUM_CORE_C0_REGS + 25) * 8, 1),
mips64_pracc.c:1003
MIPS64_LD(2, (MIPS64_NUM_CORE_C0_REGS + 26) * 8, 1),
mips64_pracc.c:1005
MIPS64_LD(2, (MIPS64_NUM_CORE_C0_REGS + 27) * 8, 1),
mips64_pracc.c:1007
MIPS64_LD(2, (MIPS64_NUM_CORE_C0_REGS + 28) * 8, 1),
mips64_pracc.c:1009
MIPS64_LD(2, (MIPS64_NUM_CORE_C0_REGS + 29) * 8, 1),
mips64_pracc.c:1011
MIPS64_LD(2, (MIPS64_NUM_CORE_C0_REGS + 30) * 8, 1),
mips64_pracc.c:1013
MIPS64_LD(2, (MIPS64_NUM_CORE_C0_REGS + 31) * 8, 1),
mips64_pracc.c:1166
MIPS64_SD(2, (MIPS64_NUM_CORE_C0_REGS + 33) * 8, 1),
mips64_pracc.c:1168
MIPS64_SD(2, (MIPS64_NUM_CORE_C0_REGS + 32) * 8, 1),
mips64_pracc.c:1170
MIPS64_SD(2, (MIPS64_NUM_CORE_C0_REGS + 34) * 8, 1),
mips64_pracc.c:1172
MIPS64_SD(2, (MIPS64_NUM_CORE_C0_REGS + 35) * 8, 1),
mips64_pracc.c:1174
MIPS64_SD(2, (MIPS64_NUM_CORE_C0_REGS + 36) * 8, 1),
mips64_pracc.c:1176
MIPS64_SD(2, (MIPS64_NUM_CORE_C0_REGS + 37) * 8, 1),
mips64_pracc.c:1178
MIPS64_SD(2, (MIPS64_NUM_CORE_C0_REGS + 0) * 8, 1),
mips64_pracc.c:1180
MIPS64_SD(2, (MIPS64_NUM_CORE_C0_REGS + 1) * 8, 1),
mips64_pracc.c:1182
MIPS64_SD(2, (MIPS64_NUM_CORE_C0_REGS + 2) * 8, 1),
mips64_pracc.c:1184
MIPS64_SD(2, (MIPS64_NUM_CORE_C0_REGS + 3) * 8, 1),
mips64_pracc.c:1186
MIPS64_SD(2, (MIPS64_NUM_CORE_C0_REGS + 4) * 8, 1),
mips64_pracc.c:1188
MIPS64_SD(2, (MIPS64_NUM_CORE_C0_REGS + 5) * 8, 1),
mips64_pracc.c:1190
MIPS64_SD(2, (MIPS64_NUM_CORE_C0_REGS + 6) * 8, 1),
mips64_pracc.c:1192
MIPS64_SD(2, (MIPS64_NUM_CORE_C0_REGS + 7) * 8, 1),
mips64_pracc.c:1194
MIPS64_SD(2, (MIPS64_NUM_CORE_C0_REGS + 8) * 8, 1),
mips64_pracc.c:1196
MIPS64_SD(2, (MIPS64_NUM_CORE_C0_REGS + 9) * 8, 1),
mips64_pracc.c:1198
MIPS64_SD(2, (MIPS64_NUM_CORE_C0_REGS + 10) * 8, 1),
mips64_pracc.c:1200
MIPS64_SD(2, (MIPS64_NUM_CORE_C0_REGS + 11) * 8, 1),
mips64_pracc.c:1202
MIPS64_SD(2, (MIPS64_NUM_CORE_C0_REGS + 12) * 8, 1),
mips64_pracc.c:1204
MIPS64_SD(2, (MIPS64_NUM_CORE_C0_REGS + 13) * 8, 1),
mips64_pracc.c:1206
MIPS64_SD(2, (MIPS64_NUM_CORE_C0_REGS + 14) * 8, 1),
mips64_pracc.c:1208
MIPS64_SD(2, (MIPS64_NUM_CORE_C0_REGS + 15) * 8, 1),
mips64_pracc.c:1210
MIPS64_SD(2, (MIPS64_NUM_CORE_C0_REGS + 16) * 8, 1),
mips64_pracc.c:1212
MIPS64_SD(2, (MIPS64_NUM_CORE_C0_REGS + 17) * 8, 1),
mips64_pracc.c:1214
MIPS64_SD(2, (MIPS64_NUM_CORE_C0_REGS + 18) * 8, 1),
mips64_pracc.c:1216
MIPS64_SD(2, (MIPS64_NUM_CORE_C0_REGS + 19) * 8, 1),
mips64_pracc.c:1218
MIPS64_SD(2, (MIPS64_NUM_CORE_C0_REGS + 20) * 8, 1),
mips64_pracc.c:1220
MIPS64_SD(2, (MIPS64_NUM_CORE_C0_REGS + 21) * 8, 1),
mips64_pracc.c:1222
MIPS64_SD(2, (MIPS64_NUM_CORE_C0_REGS + 22) * 8, 1),
mips64_pracc.c:1224
MIPS64_SD(2, (MIPS64_NUM_CORE_C0_REGS + 23) * 8, 1),
mips64_pracc.c:1226
MIPS64_SD(2, (MIPS64_NUM_CORE_C0_REGS + 24) * 8, 1),
mips64_pracc.c:1228
MIPS64_SD(2, (MIPS64_NUM_CORE_C0_REGS + 25) * 8, 1),
mips64_pracc.c:1230
MIPS64_SD(2, (MIPS64_NUM_CORE_C0_REGS + 26) * 8, 1),
mips64_pracc.c:1232
MIPS64_SD(2, (MIPS64_NUM_CORE_C0_REGS + 27) * 8, 1),
mips64_pracc.c:1234
MIPS64_SD(2, (MIPS64_NUM_CORE_C0_REGS + 28) * 8, 1),
mips64_pracc.c:1236
MIPS64_SD(2, (MIPS64_NUM_CORE_C0_REGS + 29) * 8, 1),
mips64_pracc.c:1238
MIPS64_SD(2, (MIPS64_NUM_CORE_C0_REGS + 30) * 8, 1),
mips64_pracc.c:1240
MIPS64_SD(2, (MIPS64_NUM_CORE_C0_REGS + 31) * 8, 1),