| Location | Text |
|---|
![]() log.h:152 | ![]( "Declaration") #define LOG_TARGET_INFO(target, fmt_str, ...) \ |
![]() armv8_cache.c:246 | LOG_TARGET_INFO(curr, "Wait flushing data l1."); |
![]() cortex_m.c:987 | LOG_TARGET_INFO(target, "external reset detected"); |
![]() cortex_m.c:1022 | LOG_TARGET_INFO(target, "Resuming after incorrect halt @ PC 0x%08" PRIx32 |
![]() cortex_m.c:1930 | LOG_TARGET_INFO(target, "AP write error, reset will not halt"); |
![]() cortex_m.c:2157 | LOG_TARGET_INFO(target, "only breakpoints of two bytes length supported"); |
![]() cortex_m.c:2459 | LOG_TARGET_INFO(target, "PCSR sampling not supported on this processor."); |
![]() cortex_m.c:2466 | LOG_TARGET_INFO(target, "Starting Cortex-M profiling. Sampling DWT_PCSR as fast as we can..."); |
![]() cortex_m.c:2502 | LOG_TARGET_INFO(target, "Profiling completed. %" PRIu32 " samples.", sample_count); |
![]() cortex_m.c:2797 | LOG_TARGET_INFO(target, "%s r%" PRId8 "p%" PRId8 " processor detected", |
![]() cortex_m.c:2946 | LOG_TARGET_INFO(target, "target has %d breakpoints, %d watchpoints", |
![]() esp_xtensa.c:50 | |
![]() esp_xtensa.c:135 | LOG_TARGET_INFO(target, "Detected debug stubs @ %" PRIx32, vec_addr); |
![]() esp_xtensa.c:204 | LOG_TARGET_INFO(target, "Failed to read DEBUGPC, fallback to stop-and-go"); |
![]() esp_xtensa.c:207 | LOG_TARGET_INFO(target, "NULL DEBUGPC, fallback to stop-and-go"); |
![]() esp_xtensa.c:211 | LOG_TARGET_INFO(target, "Starting XTENSA DEBUGPC profiling. Sampling as fast as we can..."); |
![]() esp_xtensa.c:243 | LOG_TARGET_INFO(target, "Profiling completed. %" PRIu32 " samples.", sample_count); |
![]() esp_xtensa_smp.c:830 | LOG_TARGET_INFO(curr, ":"); |
![]() gdb_server.c:3064 | LOG_TARGET_INFO(target, "target was not halted when resume was requested"); |
![]() gdb_server.c:3190 | LOG_TARGET_INFO(ct, "target was not halted when step was requested"); |
![]() gdb_server.c:3891 | LOG_TARGET_INFO(target, "starting gdb server on %s", port); |
![]() gdb_server.c:3925 | LOG_TARGET_INFO(target, "gdb port disabled"); |
![]() gdb_server.c:3932 | LOG_TARGET_INFO(target, "gdb port disabled"); |
![]() target.c:690 | LOG_TARGET_INFO(target, "Examination succeed"); |
![]() target.c:3288 | LOG_TARGET_INFO(target, "requesting target halt and executing a soft reset"); |
![]() xtensa.c:2235 | LOG_TARGET_INFO(target, "Disabling LDDR32.P/SDDR32.P"); |
![]() xtensa.c:2323 | LOG_TARGET_INFO(target, "Debug controller was reset."); |
![]() xtensa.c:2329 | LOG_TARGET_INFO(target, "Core was reset."); |
![]() xtensa.c:2426 | LOG_TARGET_INFO(target, "Trace stop triggered by PC match"); |
![]() xtensa.c:2428 | LOG_TARGET_INFO(target, "Trace stop triggered by Processor Trigger Input"); |
![]() xtensa.c:2430 | LOG_TARGET_INFO(target, "Trace stop triggered by Cross-trigger Input"); |