Defines the root entity used to generate FPGA bitstream and specifies the port mapping in the UCF file.

synthesize_hardware<"FPGA name"> EntityName(
    port1 = "pin map 1",
    ...,
    portN = "pin map N"
);

synthesize_hardware<"FPGA name"> EntityName(
    port1 = "pin map 1",
    ...,
    portN = "pin map N"
) post_route_sim(PostRouteTestbenchEntity);

The FPGA name specified in this statement will be passed directly to the underlying toolchain (e.g. Xilinx XST). The pin mapping is used to generate the UCF file. Note that you can insert arbitrary lines to the UCF file by putting __ucf() statements in THDL++ files.

PIN1,PIN2,...,PINx
modifier1,...,modifierN:PIN1,PIN2,...,PINx

Modifier	UCF equivalent
up	PULLUP
down	PULLDOWN
slow	SLEW = "SLOW"
fast	SLEW = "FAST"
d=N	DRIVE = "N"
Any string in square brackets, e.g. [IOSTANDARD = SSTL18_II]	directly copied to UCF file

Every time an FPGA-targeted configuration is built all source files are scanned for synthesize_hardware statements. The entity specified in the statement will be used as the root entity. If you are building a post-route simulation configuration, the post_route_sim clause should also be specified; otherwise it will be ignored.

If none or multiple statements are found, an error is raised. Use the #ifdef statements to ensure that every configuration has one and only one synthesize_hardware statement. Note that synthesize_hardware statements will be ignored when building behavioral simulation configurations.

synthesize_hardware<"xc3s700an-fgg484-4"> LEDBlinkDemo(
    clk="E12",
    LEDs="W21,Y22,V20,V19,U19,U20,T19,R20");

Generated UCF file:

NET "thp_n0000_clk" LOC = "E12";
NET "thp_n0001_LEDs<7>" LOC = "W21";
NET "thp_n0001_LEDs<6>" LOC = "Y22";
NET "thp_n0001_LEDs<5>" LOC = "V20";
NET "thp_n0001_LEDs<4>" LOC = "V19";
NET "thp_n0001_LEDs<3>" LOC = "U19";
NET "thp_n0001_LEDs<2>" LOC = "U20";
NET "thp_n0001_LEDs<1>" LOC = "T19";
NET "thp_n0001_LEDs<0>" LOC = "R20";

synthesize_hardware<"XC5VFX70T-FF1136-1"> FTDIConnectionTester(
    sclk="L19",
    OData="d=8,slow:R34,T33,N32,P32,K33,L34,K32,K34");

Generated UCF file:

NET "sclk" LOC = "L19";
NET "OData<7>" LOC = "R34" | DRIVE = "8" | SLEW = "SLOW";
NET "OData<6>" LOC = "T33" | DRIVE = "8" | SLEW = "SLOW";
NET "OData<5>" LOC = "N32" | DRIVE = "8" | SLEW = "SLOW";
NET "OData<4>" LOC = "P32" | DRIVE = "8" | SLEW = "SLOW";
NET "OData<3>" LOC = "K33" | DRIVE = "8" | SLEW = "SLOW";
NET "OData<2>" LOC = "L34" | DRIVE = "8" | SLEW = "SLOW";
NET "OData<1>" LOC = "K32" | DRIVE = "8" | SLEW = "SLOW";
NET "OData<0>" LOC = "K34" | DRIVE = "8" | SLEW = "SLOW";

synthesize_hardware<"XC5VFX70T-FF1136-1"> FTDIConnectionTester(
    sclk="L19",
    OData="d=8,[IOSTANDARD = SSTL18_II],slow:R34,T33,N32,P32,K33,L34,K32,K34");

Generated UCF file:

NET "sclk" LOC = "L19";
NET "OData<7>" LOC = "R34" | DRIVE = "8" | IOSTANDARD = SSTL18_II | SLEW = "SLOW";
NET "OData<6>" LOC = "T33" | DRIVE = "8" | IOSTANDARD = SSTL18_II | SLEW = "SLOW";
NET "OData<5>" LOC = "N32" | DRIVE = "8" | IOSTANDARD = SSTL18_II | SLEW = "SLOW";
NET "OData<4>" LOC = "P32" | DRIVE = "8" | IOSTANDARD = SSTL18_II | SLEW = "SLOW";
NET "OData<3>" LOC = "K33" | DRIVE = "8" | IOSTANDARD = SSTL18_II | SLEW = "SLOW";
NET "OData<2>" LOC = "L34" | DRIVE = "8" | IOSTANDARD = SSTL18_II | SLEW = "SLOW";
NET "OData<1>" LOC = "K32" | DRIVE = "8" | IOSTANDARD = SSTL18_II | SLEW = "SLOW";
NET "OData<0>" LOC = "K34" | DRIVE = "8" | IOSTANDARD = SSTL18_II | SLEW = "SLOW";

synthesize_hardware<"xc3s700an-fgg484-4"> LEDBlinkDemo(
    clk="E12",
    LEDs="W21,Y22,V20,V19,U19,U20,T19,R20"
) post_route_sim(SimulatedClockProvider<20ns, LEDBlinkDemo>);

Generated entities:

For FPGA-targeted configurations the result will be equivalent to example 1. For post-route simulation configurations VisualHDL will generate FPGA layout with LEDBlinkDemo being the root entity and then generate a post-route ISim-based simulation using SimulatedClockProvider<20ns, LEDBlinkDemo> as the testbench. Note that all instances of LEDBlinkDemo inside SimulatedClockProvider<20ns, LEDBlinkDemo> will be replaced by the post-route simulation model generated by netgen. If the entity specified in post_route_sim does not contain an instance of the root entity specified in synthesize_hardware, VisualHDL will show an error and fail the build.