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<page id="simulate_entity" suffix=" Statement">
  <subsection>Defines the testbench entity used for behavioral simulation.<code>simulate_entity(EntityName);</code></subsection>
  <section name="Remarks">
    <p>Every time a simulator-targeted configuration is built all source files are scanned for <kw>simulate_entity</kw> statements. The entity specified in the statement will be used as the root (testbench) entity. Note that the entity specified in the <kw>simulate_entity</kw> statement should normally contain process generating your clock(s). </p>
  </section>
  <section name="Advice">
    <p>You don't have to write clock generation code every time! See the examples section for more details.</p>
  </section>
  <examples>
  <example name="Custom testbench"><code>simulate_entity(MyTestbenchName);</code></example>
  <example name="Using generic clock generator."><p>
If you want to use the same testbench in the simulator and on the FPGA, you can declare an entity with an input port called "clk" and use Core.SimulatedClockProvider as the testbench.</p>
<code>simulate_entity(SimulatedClockProvider&lt;20ns, MyEntityWithClkInput&gt;);</code>
	</example>
	<example name="Inheriting clock generation code">
<p>You can reuse clock generation code in your testbench by inheriting Core.SimulatedClockBase entity. E.g.:</p>
			<code>entity MyTestbench : SimulatedClockBase&lt;10ns&gt;
{
	LEDBlinkDemo uut(
		clk = clk,
		LEDs = auto
	);
}

simulate_entity(MyTestbench);</code>
			<p>By inheriting SimulatedClockBase the MyTestbench entity automatically receives a "clk" signal with the period specified as SimulatedClockBase template argument.</p>
	</example>
</examples>
<seealso id="synthesize_hardware"/>
<seealso id="generate_vhdl"/>
</page>