Describes a multiplexer. Similar to the switch statement. Can be used inside an implicit/explicit process or a function.

SignalOrVar = select(Expression)
{
	case Val1:
	case Val2:
		AssignedExpr1;
	case Val3:
		AssignedExpr2;
		break;
	case ValN:
		...
		break;
	default:
		AssignedExprN;
		break;
}

The select statement can be specified inside a process or function. It uses C++ syntax and will be directly converted to a VHDL case statement.

The select statement is a shorter form of a switch statement where every case expression assigns the same variable or signal.

If the expression used in the select statement is of an enumeration type and you want to ensure that all cases have been considered, use the selectall statement.

entity SomeFSM
{
	enum State
	{
		Initial,
		Reading,
		Writing,
	}
	
    signal State CurrentState = State.Initial;
    signal logic[8] StateCode;
    
    StateCode = select(CurrentState)
    {
    	case State.Initial:
    	case State.Reading: 1;
    	case State.Writing: 2;
    };
}

Generated VHDL code:

entity Some_FSM is
end entity Some_FSM;

architecture Behavioral of Some_FSM is
	signal Current_State : Some_FSM_State := Initial;
	signal State_Code : std_logic_vector(7 downto 0);
	
	begin
		State_Code <= X"01" when ((Current_State = Initial)) or ((Current_State = Reading))
			else X"02" when ((Current_State = Writing));
		
end architecture Behavioral;