Defines a process.

process ProcessName(sensitivity_list)
{
	Process_contents;
}

THDL++ processes have full semantics of VHDL processes. Moreover, every THDL++ process will be compiled, line-by-line, into a corresponding VHDL process. The syntax of THDL++ process bodies is similar to functions. THDL++ processes can have explicit sensitivity lists, just like in VHDL. Additionally to that, there are two special syntax forms that simplify most of the use cases:

Sensitivity to all inputs. To make a process sensitive to all inputs, specify any keyword inside the sensitivity list.
Sensitivity to a clock. To make a process sensitive to rising/falling edge of a clock, specify clock_name.rising or clock_name.falling in the sensitivity list.

An entity can also have implicit processes similar to VHDL ones. An implicit process has the following syntax: sig_name = expression;

If a process is sensitive to a clock, you can use the autoreset keyword to generate a block that will assign default values to all signals modified by the process in case the reset signal goes high or low. See the autoreset page for more details.

entity Test
{
	signal logic[8] a, b, c;
	
	process test (any)
	{
		a = b + c;
	}
}

The following VHDL code will be generated:

entity Test is
end entity Test;

architecture Behavioral of Test is
	signal a : std_logic_vector(7 downto 0);
	signal b : std_logic_vector(7 downto 0);
	signal c : std_logic_vector(7 downto 0);
	
	begin
		test : process (b, c) is
		begin
			a <= (b + c);
		end process test;
		
end architecture Behavioral;

entity Test
{
	signal logic[8] a, b, c;
	port in logic clk;
	
	process test (clk.rising)
	{
		a = b + c;
	}
}

Generated VHDL code:

entity Test is
	Port (
		clk : in std_logic
	);
	
end entity Test;

architecture Behavioral of Test is
	signal a : std_logic_vector(7 downto 0);
	signal b : std_logic_vector(7 downto 0);
	signal c : std_logic_vector(7 downto 0);
	
	begin
		test : process (clk) is
		begin
			if rising_edge(clk) then
				a <= (b + c);
			end if;
		end process test;
		
end architecture Behavioral;

entity Test
{
	signal logic clk = '0';
	
	process test ()
	{
		clk = !clk;
		wait(10ns);
	}
}

Generated VHDL code:

entity Test is
end entity Test;

architecture Behavioral of Test is
	signal clk : std_logic := '0';
	
	begin
		test : process  is
		begin
			clk <= (not clk);
			wait for 10ns;
		end process test;
		
end architecture Behavioral;