Declares a port.port in/out/inout TypeName PortName; The port keyword declares a port in an entity. Ports can be declared in arbitrary order and can be grouped to improve readability. Port semantics in THDL++ is equivalent to VHDL. See examples for more details.

It is recommended to avoid hardcoding port types when you declare entities. Instead, use typedef statements or template arguments.

Sometimes you can increase readability of your port declarations using compact entity declaration syntax. See the entity page for more details.

THDL++ ports can have initial values. For input ports initial values will be used if the port is omited in the port map. For output ports the values will be assigned to the ports before the first assignment statement changes it. See examples for details.

In THDL++ you can read the values of output ports! When generating VHDL, shadow signals will be created automatically.

entity Adder
{
	port in logic[8] X = 0, Y = 0;
	port out logic[8] Result;
	
	Result = X + Y;
}

The following code is also valid, however, is much less readable:

entity Adder
{
	port in logic[8] X, Y;
	
	Result = X + Y;

	port out logic[8] Result;
}

entity Adder
{
	port
	{
		in logic[8] X, Y;
		out logic[8] Result;
	}

	Result = X + Y;
}

entity Adder
{
	typedef logic[8] DataType;
	port
	{
		in DataType X, Y;
		out DataType Result;
	}

	Result = X + Y;
}

entity Counter
{
	port in logic clk, reset;
	port out logic[8] Value = 0;
	
	process sync (clk.rising) autoreset(reset)
	{
		Value++;
	}
}

The following VHDL code will be generated:

entity Counter is
	Port (
		clk : in std_logic;
		reset : in std_logic;
		Value : out std_logic_vector(7 downto 0)
	);
	
end entity Counter;

architecture Behavioral of Counter is
	signal thp_shadow_Value : std_logic_vector(7 downto 0) := X"00";
	
	begin
		Value <= thp_shadow_Value;
		
		sync : process (clk, reset) is
		begin
			if reset = '1' then
				Value <= X"00";
			elsif rising_edge(clk) then
				thp_shadow_Value <= (thp_shadow_Value + X"01");
			end if;
		end process sync;
		
end architecture Behavioral;