link TypeName SigName = Expression;
If you try to declare a normal
You don't have to specify the type of the signal when using
entity Test
{
port in logic[8] X, Y;
signal logic[8] sum;
sum = X + Y;
}
The following VHDL code will be generated:
entity Test is
Port (
X : in std_logic_vector(7 downto 0);
Y : in std_logic_vector(7 downto 0)
);
end entity Test;
architecture Behavioral of Test is
signal sum : std_logic_vector(7 downto 0);
begin
sum <= (X + Y);
end architecture Behavioral;
You could achieve the same result by using entity Test
{
port in logic[8] X, Y;
link logic[8] sum = X + Y;
}
The generated VHDL code will be exactly the same.
entity Test
{
port in logic[8] X, Y;
link auto sum = X + Y;
}
The type of sum will be inferred from the "X + Y" expression.