Declares a signal and creates an implicit process.link TypeName SigName = Expression; The link statement is equivalent to a signal statement followed by an implicit process. See examples for more details.

If you try to declare a normal signal with a non-constant initial value, THDL++ compiler will show an error message and suggest using the link statement instead.

You don't have to specify the type of the signal when using link statements. If you use the auto or any keyword instead, the type will be inferred from the expression on the right.

Let's define a signal sum thats value should be always equivalent to X + Y:

entity Test
{
	port in logic[8] X, Y;
	
	signal logic[8] sum;
	sum = X + Y;
}

The following VHDL code will be generated:

entity Test is
	Port (
		X : in std_logic_vector(7 downto 0);
		Y : in std_logic_vector(7 downto 0)
	);
	
end entity Test;

architecture Behavioral of Test is
	signal sum : std_logic_vector(7 downto 0);
	
	begin
		sum <= (X + Y);
end architecture Behavioral;

You could achieve the same result by using link statement instead:

entity Test
{
	port in logic[8] X, Y;
	link logic[8] sum = X + Y;
}

The generated VHDL code will be exactly the same. The following code is equivalent to the previous example:

entity Test
{
	port in logic[8] X, Y;
	link auto sum = X + Y;
}

The type of sum will be inferred from the "X + Y" expression.