Makes an entity described in VHDL visible for THDL++ code.import_entity EntityName("filename.vhd");

The import_entity statement allows instantiating existing VHDL entities inside THDL++ entities. To do the reverse, use the generate_vhdl statement.

Note that the current implementation import_entity won't be able to parse an entity declaration if it has generic port widths. To avoid it, please make wrapper entities with fixed-size ports around generic VHDL entities to import them to THDL++ code.

The import_entity statement does not automatically add the referenced file to the project. This behavior is similar to forward declarations in C/C++. Always add the related VHDL files to the project if you want VisualHDL to build them correctly.

import_entity Multiplier("multiplier.vhd");

entity Squarer
{
	port in logic[8] X;
	port out logic[16] Y; 

	Multiplier mul
	(
		a = X,
		b = X,
		y = Y
	); 
}

entity MyTestbench
{
	port in logic clk;
	
	Squarer uut(
		X = auto(0),
		Y = auto
	);
	
	process count (clk.rising)
	{
		uut.X += 1;
	}
}

simulate_entity(SimulatedClockProvider<20ns, MyTestbench>);