Specifies additional entities that will be compiled to VHDL.generate_vhdl(EntityName);

Normally, VisualHDL uses either synthesize_hardware or simulate_entity to determine the root entity of your design. Then it generates VHDL code for the root entity and all entities referenced by it. However, you can additionally generate VHDL code for any other entities of your choice. To do so, use the generate_vhdlstatement.

using Core.Primitives;
using Core.RAMs.Synchronous;
	
entity LEDSetter
{
	port out logic[8] LEDs;

	LEDs = 0x55;
}

entity MyTestbench
{
	LEDSetter uut(
		LEDs = auto
	);
}

simulate_entity(MyTestbench);
generate_vhdl(SimpleRAM<1024, 8>);
generate_vhdl(SimpleRAM<512, 16>);

This code will generate VHDL for MyTestbench, LEDSetter and two variations of SimpleRAM.