Describes a block of entity contents that is repeating or conditionally present.generate Block_Name for(init; condition; increment) { Generate_contents; } generate Block_Name foreach(any Iterator_name in List_name) { Generate_contents; } generate Block_Name if (Condition1) { Generate_contents_1; } else if (Condition2) { Generate_contents_2; } else { Generate_contents_3; } The generate statements can contain the following primitives inside: typedef, const, signal, link, process, generate and instances of entities. All generate block should be named.

You can access the signals and instances declared inside a generate block through the name of the block. E.g. MyGenerateForeachName[0].Sig1

Combining the generate statements with auto signals (see entity) could be useful in making generic designs.

When using the foreach form of generate, the __foreach_iteration variable contains the current iteration number.

In this example we will sketch a generic description of an MCU containing several peripherals. By modifying the peripheral list you will be able to add or remove peripherals without changing other code. Every peripheral has a clock input, 8-bit address input and a data output. The 4 most-significant of the address bits define which peripheral is being addressed. Here's a sample definition of a peripheral: entity IPCore1 { const int AddrBase = 2; port { in logic clk; in logic[4] Addr; out logic[8] Data; } } The AddrBase defines the value of the 4 most-significant address bits that correspond to the peripheral. We will define a multiplexer based on that.
Let's make a generic MCU entity: template <any _Peripherals> entity MCU { signal { logic clk; logic[8] Addr; logic[8] Data; } generate instances foreach(any p in _Peripherals) { p instance( clk = clk, Addr = Addr[3 to 0], Data = auto); } } Let's now generate VHDL for an MCU containing 2 peripherals: generate_vhdl(MCU<__list(IPCore1, IPCore2)>); Generated VHDL code: architecture Behavioral of MCU_list_IPCore1_IPCore2 is signal clk : std_logic; signal Addr : std_logic_vector(7 downto 0); signal Data : std_logic_vector(7 downto 0); signal instances_0_thp_instance_autosig_Data : std_logic_vector(7 downto 0); signal instances_1_thp_instance_autosig_Data : std_logic_vector(7 downto 0); component IPCore1 is Port ( clk : in std_logic; Addr : in std_logic_vector(3 downto 0); Data : out std_logic_vector(7 downto 0) ); end component IPCore1; component IPCore2 is Port ( clk : in std_logic; Addr : in std_logic_vector(3 downto 0); Data : out std_logic_vector(7 downto 0) ); end component IPCore2; begin instances_0_instance : IPCore1 port map ( clk => clk, Addr => Addr(3 downto 0), Data => instances_0_thp_instance_autosig_Data ); instances_1_instance : IPCore2 port map ( clk => clk, Addr => Addr(3 downto 0), Data => instances_1_thp_instance_autosig_Data ); end architecture Behavioral; Now let's describe a multiplexer selecting the value of Data from a peripheral corresponding to current 4 most-significant bits of Addr: process SelectData (any) { Data = '-'; for(int i = 0; i lt sizeof(instances); i++) if (Addr[7 to 4] == typeof(instances[i].instance).AddrBase) Data = instances[i].instance.Data; } Let's look through the code line-by-line:
  1. Assign the default value for Data: Data = '-';
  2. Run i from 0 to number of times the generate block was unrolled. "instances" is the name of the block. for(int i = 0; i lt sizeof(instances); i++)
  3. Compare most-significant bits of Addr with the AddrBase constant defined in a corresponding entity: if (Addr[7 to 4] == typeof(instances[i].instance).AddrBase) Let's have a detailed look here:
    • "instances[i]" means "the i-th instance of the instances block".
    • "instances[i].instance" means object named "instance" inside the i-th instance of the block. "instance" was the name of the entity instance (see the body of the generate block above).
    • Writing "instances[i].instance.AddrBase" would be wrong, as the instance itself does not declare any constants. The constant was instead declared in a corresponding entity. We can get the entity of an instance by using the typeof() function.
    • "typeof(instances[i].instance)" means the entity used to create i-th instance. E.g. typeof(instances[0].instance) will be IPCore1, as it's the first entity in the list that will be used to generate the first instance of the generate block.
    • Finally, "typeof(instances[i].instance).AddrBase" the constant "AddrBase" declared in the corresponding entity.
  4. Assign Data to the Data output of the corresponding instance: Data = instances[i].instance.Data;
Generated VHDL code for the process: SelectData : process (Addr, instances_0_thp_instance_autosig_Data, instances_1_thp_instance_autosig_Data) is begin Data <= (others => '-'); if (Addr(7 downto 4) = X"2") then Data <= instances_0_thp_instance_autosig_Data; end if; if (Addr(7 downto 4) = X"5") then Data <= instances_1_thp_instance_autosig_Data; end if; end process SelectData; template <bool _SquareResult> entity DistanceCalculator { port in logic[8] A, B; port out logic[8] Result; link auto tmp = A - B; generate main if(_SquareResult) { Squarer inst( X = tmp, Y = Result ); } else { Result = tmp; } } Let's generate VHDL for the case when _SquareResult is true: generate_vhdl(DistanceCalculator<true>); Generated VHDL code: entity Distance_Calculator_True is Port ( A : in std_logic_vector(7 downto 0); B : in std_logic_vector(7 downto 0); Result : out std_logic_vector(7 downto 0) ); end entity Distance_Calculator_True; architecture Behavioral of Distance_Calculator_True is signal tmp : std_logic_vector(7 downto 0); component Squarer is Port ( X : in std_logic_vector(7 downto 0); Y : out std_logic_vector(7 downto 0) ); end component Squarer; begin main_case_1_inst : Squarer port map ( X => tmp, Y => Result ); tmp <= (A - B); end architecture Behavioral;