Performs the zero extension of a logic vector logic[y] extend_zero(logic[x] vec, int y);

entity Test
{
	signal logic[8] a;
	signal logic[16] b;

	b = extend_zero(a, 16);
}

Generated VHDL code:

entity Test is
end entity Test;

architecture Behavioral of Test is
	signal a : std_logic_vector(7 downto 0);
	signal b : std_logic_vector(15 downto 0);
	
	begin
		b <= (X"00" & a);
		
end architecture Behavioral;