logic[y] extend_sign(logic[x] vec, int y);
entity Test
{
signal logic[8] a;
signal logic[16] b;
b = extend_sign(a, 16);
}
Generated VHDL code:
entity Test is
end entity Test;
architecture Behavioral of Test is
signal a : std_logic_vector(7 downto 0);
signal b : std_logic_vector(15 downto 0);
begin
b <= (thp_ite_1((a(7) = '1'), X"FF", X"00")(7 downto 0) & a);
end architecture Behavioral;