process ProcessName(clk.rising) autoreset(reset_signal_name)
{
Process_contents;
}
THDL++ compiler can automatically generate reset blocks for processes. A reset block will activate when the reset signal becomes high (or low if "!" was specified). The reset block will assign initial values (specified in signal declarations) to all signals written by the process.
If a process has an autoreset statement, it should be sensitive to a rising/falling edge of a clock signal and all signals written by the process should have initial values in the declarations. Otherwise, an error message will be shown.
If a process contains range assignment statements (e.g. sig1[0] = '0'), the autoreset block will not be generated and an error message will be shown.
entity Counter
{
port in logic clk, reset;
port out logic[8] Value = 0;
process sync (clk.rising) autoreset(reset)
{
Value++;
}
}
The following VHDL code will be generated:
entity Counter is
Port (
clk : in std_logic;
reset : in std_logic;
Value : out std_logic_vector(7 downto 0)
);
end entity Counter;
architecture Behavioral of Counter is
signal thp_shadow_Value : std_logic_vector(7 downto 0) := X"00";
begin
Value <= thp_shadow_Value;
sync : process (clk, reset) is
begin
if reset = '1' then
Value <= X"00";
elsif rising_edge(clk) then
thp_shadow_Value <= (thp_shadow_Value + X"01");
end if;
end process sync;
end architecture Behavioral;
To make the reset signal active-low, simply prefix it with "!" in the process sync (clk.rising) autoreset(!reset)