Attributes allow placing compile-time "tags" on ports, signals, entities, classes, etc. and writing generic code iterating through all ports/signals/etc. having a certain tag. E.g. it is possible to mark certain ports of a component as "exported" and then write a generic process making the values of all "exported" ports available through a bus.

[Attribute1, Attribute2, ..., AttributeN]
class/entity/port/etc
{
	...
}

Every attribute should be a class derived from System.Attributes.Attribute. To get a list (see lists) of all attributes of a certain primitive, use the __attributes built-in function. To get all ports of an entity (or an instance) having a specified attribute, use the __ports built-in function.

THDL++ defines the following built-in attributes: This attribute disables name all transformations made by VHDL generator and ensures that VHDL port/signal name exactly matches THDL++ port/signal name. Example:

entity Test
{
	signal logic TestSig1;
	
	[System.Attributes.ExactNaming]
	signal logic TestSig2;
}

Generated code:

architecture Behavioral of Test is
	signal Test_Sig1 : std_logic;
	signal TestSig2 : std_logic;
	
	begin
		
end architecture Behavioral;

The signal TestSig1 has been converted to Test_Sig1 to improve simulation experience with ISim (ISim converts all signal names to lowercase). Specifying ExactNaming on TestSig2 prevented this.

Let's sketch a generic wrapper that makes all desired ports of an entity accessible through a bus. First, let's define our attribute class: class MyExportable : System.Attributes.Attribute {} The class is empty. It is only used to tag something with "MyExportable" and to lookup "everything tagged with MyExportable".
Now let's define an entity having several ports (A, B and D) tagged with MyExportable:

entity MyTestedEntity
{
	port in logic clk;
	[MyExportable]
	port out logic [8] A, B;
	port out logic[8] C;
		
	[MyExportable]
	port out logic[8] D;
}

Let's also write a wrapper entity:

entity Test
{
	signal logic clk;
	
	MyTestedEntity uut(
		clk = clk,
		A = auto,
		B = auto,
		C = auto,
		D = auto
	);
	
	port in logic[8] Addr;
	port out logic[8] Data;
}

Finally, let's use attributes! We will define a generic process that allows reading exportable registers using the Addr/Data ports:

	process route (any)
	{
		Data = '-';
		foreach(any s in __ports(uut, MyExportable))
			if (Addr == __foreach_iteration)
				Data = s;
	}

Generated VHDL code:

		uut : My_Tested_Entity
			port map (
				clk => clk,
				A => thp_uut_autosig_A,
				B => thp_uut_autosig_B,
				C => thp_uut_autosig_C,
				D => thp_uut_autosig_D
			);
		
		route : process (Addr, thp_uut_autosig_A, thp_uut_autosig_B, thp_uut_autosig_D) is
		begin
			Data <= (others => '-');
			if (Addr = X"00") then
				Data <= thp_uut_autosig_A;
			end if;
			if (Addr = X"01") then
				Data <= thp_uut_autosig_B;
			end if;
			if (Addr = X"02") then
				Data <= thp_uut_autosig_D;
			end if;
		end process route;

Let's modify the previous example to specify the bus address of each port when declaring the ports: template <int Addr> class MyExportable : System.Attributes.Attribute { } The port declaration will now look the following way:

	port in logic clk;
	[MyExportable<0>]
	port out logic [8] A;
	[MyExportable<2>]
	port out logic [8] B;
	port out logic[8] C;
		
	[MyExportable<5>]
	port out logic[8] D;

Finally, the route process will have to be modified:

process route (any)
{
	Data = '-';
	foreach(any s in __ports(uut))
	{
		foreach (any a in __attributes(s))
			if (__defined(a.Addr))
				if (Addr == a.Addr)
					Data = s;
	}
}