The any keyword can be used in two scenarios:

Inside a sensitivity list to make a process sensitive to all inputs. See process page for more details.
Instead of a variable/link type to have the type inferred automatically.

When used as a type name, the any keyword is equivalent to the auto keyword.

entity Test
{
	signal logic[8] a, b, c;
	
	process test (any)
	{
		a = b + c;
	}
}

The following VHDL code will be generated:

entity Test is
end entity Test;

architecture Behavioral of Test is
	signal a : std_logic_vector(7 downto 0);
	signal b : std_logic_vector(7 downto 0);
	signal c : std_logic_vector(7 downto 0);
	
	begin
		test : process (b, c) is
		begin
			a <= (b + c);
		end process test;
		
end architecture Behavioral;

	signal logic[8] a, b, c;
    process test (clk.rising)
    {
    	any tmp = a cat b;
    	c = tmp[12 to 5];
    }

Generated VHDL code:

		test : process (clk) is
			variable tmp : std_logic_vector(15 downto 0);
		begin
			if rising_edge(clk) then
				tmp := (a & b);
				c <= tmp(12 downto 5);
			end if;
		end process test;

The type of the variable "tmp" has been derived from the "a cat b" expression.