Checks if a port is writable. bool __writable(any port) The __writable() will return true for out/inout ports and false otherwise. When used with auto signals (see entity, it will return true for in/inout ports (thus writable by the outer entity) and false for out ports).

entity Test
{
	port in logic[8] X;
	port out logic[8] Y;
	port in logic clk;

	process step (clk.rising)
	{
		foreach(any p in __ports(Test))
			if (__writable(p))
				p++;
	}	
}

Generated VHDL code:

entity Test is
	Port (
		X : in std_logic_vector(7 downto 0);
		Y : out std_logic_vector(7 downto 0);
		clk : in std_logic
	);
	
end entity Test;

architecture Behavioral of Test is
	signal thp_shadow_Y : std_logic_vector(7 downto 0);
	
	begin
		Y <= thp_shadow_Y;
		
		step : process (clk) is
		begin
			if rising_edge(clk) then
				thp_shadow_Y <= (thp_shadow_Y + X"01");
			end if;
		end process step;
		
		
end architecture Behavioral;