Allows building lists of signals to use them from generic code. __list(__decl(sig1), __decl(sig2), ...) The __decl() function should be used when declaring lists of signals to use them inside for/foreach statements.

entity Test
{
	signal
	{
		logic[8] a;
		logic[16] b;
		int c;
		
		logic clk;
	}

	process count (clk.rising)
	{
		foreach(any sig in __list(__decl(a), __decl(b), __decl(c)))
			sig++;
	}	
}

Generated VHDL code:

entity Test is
end entity Test;

architecture Behavioral of Test is
	signal a : std_logic_vector(7 downto 0);
	signal b : std_logic_vector(15 downto 0);
	signal c : integer;
	signal clk : std_logic;
	
	begin
		count : process (clk) is
		begin
			if rising_edge(clk) then
				a <= (a + X"01");
				b <= (b + X"0001");
				c <= (c + 1);
			end if;
		end process count;
		
end architecture Behavioral;

Note that omitting __decl keyword (e.g. __list(a,b,c)) would cause errors, as normally the values of list contents should be known at compile-time.