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/* ... */
#include "stm32f4xx_hal.h"
#include "lwip/timeouts.h"
#include "netif/ethernet.h"
#include "netif/etharp.h"
#include "lwip/stats.h"
#include "lwip/snmp.h"
#include "lwip/tcpip.h"
#include "ethernetif.h"
#include "../Components/dp83848/dp83848.h"
#include <string.h>
10 includes
Includes
#define IFNAME0 's'
#define IFNAME1 't'
#define ETH_DMA_TRANSMIT_TIMEOUT (20U)
#define ETH_RX_BUFFER_CNT 10
/* ... */
#define ETH_TX_BUFFER_MAX ((ETH_TX_DESC_CNT) * 2)
/* ... */
Private define
/* ... */
typedef enum
{
RX_ALLOC_OK = 0x00,
RX_ALLOC_ERROR = 0x01
...} RxAllocStatusTypeDef;
typedef struct
{
struct pbuf_custom pbuf_custom;
uint8_t buff[(ETH_RX_BUF_SIZE + 31) & ~31] __ALIGNED(32);
...} RxBuff_t;
ETH_DMADescTypeDef DMARxDscrTab[ETH_RX_DESC_CNT];
ETH_DMADescTypeDef DMATxDscrTab[ETH_TX_DESC_CNT];
LWIP_MEMPOOL_DECLARE(RX_POOL, ETH_RX_BUFFER_CNT, sizeof(RxBuff_t), "Zero-copy RX PBUF pool");
static uint8_t RxAllocStatus;
ETH_HandleTypeDef EthHandle;
ETH_TxPacketConfig TxConfig;
dp83848_Object_t DP83848;
Private variables
extern void Error_Handler(void);
int32_t ETH_PHY_IO_Init(void);
int32_t ETH_PHY_IO_DeInit (void);
int32_t ETH_PHY_IO_ReadReg(uint32_t DevAddr, uint32_t RegAddr, uint32_t *pRegVal);
int32_t ETH_PHY_IO_WriteReg(uint32_t DevAddr, uint32_t RegAddr, uint32_t RegVal);
int32_t ETH_PHY_IO_GetTick(void);
void pbuf_free_custom(struct pbuf *p);
dp83848_IOCtx_t DP83848_IOCtx = {ETH_PHY_IO_Init,
ETH_PHY_IO_DeInit,
ETH_PHY_IO_WriteReg,
ETH_PHY_IO_ReadReg,
ETH_PHY_IO_GetTick...};Private function prototypes
/* ... */
/* ... */
static void low_level_init(struct netif *netif)
{
uint8_t macaddress[6]= {ETH_MAC_ADDR0, ETH_MAC_ADDR1, ETH_MAC_ADDR2, ETH_MAC_ADDR3, ETH_MAC_ADDR4, ETH_MAC_ADDR5};
EthHandle.Instance = ETH;
EthHandle.Init.MACAddr = macaddress;
EthHandle.Init.MediaInterface = HAL_ETH_MII_MODE;
EthHandle.Init.RxDesc = DMARxDscrTab;
EthHandle.Init.TxDesc = DMATxDscrTab;
EthHandle.Init.RxBuffLen = ETH_RX_BUF_SIZE;
HAL_ETH_Init(&EthHandle);
netif->hwaddr_len = ETH_HWADDR_LEN;
netif->hwaddr[0] = ETH_MAC_ADDR0;
netif->hwaddr[1] = ETH_MAC_ADDR1;
netif->hwaddr[2] = ETH_MAC_ADDR2;
netif->hwaddr[3] = ETH_MAC_ADDR3;
netif->hwaddr[4] = ETH_MAC_ADDR4;
netif->hwaddr[5] = ETH_MAC_ADDR5;
netif->mtu = ETH_MAX_PAYLOAD;
netif->flags |= NETIF_FLAG_BROADCAST | NETIF_FLAG_ETHARP;
LWIP_MEMPOOL_INIT(RX_POOL);
memset(&TxConfig, 0 , sizeof(ETH_TxPacketConfig));
TxConfig.Attributes = ETH_TX_PACKETS_FEATURES_CSUM | ETH_TX_PACKETS_FEATURES_CRCPAD;
TxConfig.ChecksumCtrl = ETH_CHECKSUM_IPHDR_PAYLOAD_INSERT_PHDR_CALC;
TxConfig.CRCPadCtrl = ETH_CRC_PAD_INSERT;
DP83848_RegisterBusIO(&DP83848, &DP83848_IOCtx);
DP83848_Init(&DP83848);
ethernet_link_check_state(netif);
}{ ... }
/* ... */
static err_t low_level_output(struct netif *netif, struct pbuf *p)
{
uint32_t i = 0U;
struct pbuf *q = NULL;
err_t errval = ERR_OK;
ETH_BufferTypeDef Txbuffer[ETH_TX_DESC_CNT] = {0};
memset(Txbuffer, 0 , ETH_TX_DESC_CNT*sizeof(ETH_BufferTypeDef));
for(q = p; q != NULL; q = q->next)
{
if(i >= ETH_TX_DESC_CNT)
return ERR_IF;
Txbuffer[i].buffer = q->payload;
Txbuffer[i].len = q->len;
if(i>0)
{
Txbuffer[i-1].next = &Txbuffer[i];
}if (i>0) { ... }
if(q->next == NULL)
{
Txbuffer[i].next = NULL;
}if (q->next == NULL) { ... }
i++;
}for (q = p; q != NULL; q = q->next) { ... }
TxConfig.Length = p->tot_len;
TxConfig.TxBuffer = Txbuffer;
TxConfig.pData = p;
HAL_ETH_Transmit(&EthHandle, &TxConfig, ETH_DMA_TRANSMIT_TIMEOUT);
return errval;
}{ ... }
/* ... */
static struct pbuf * low_level_input(struct netif *netif)
{
struct pbuf *p = NULL;
if(RxAllocStatus == RX_ALLOC_OK)
{
HAL_ETH_ReadData(&EthHandle, (void **)&p);
}if (RxAllocStatus == RX_ALLOC_OK) { ... }
return p;
}{ ... }
/* ... */
void ethernetif_input(struct netif *netif)
{
struct pbuf *p = NULL;
do
{
p = low_level_input( netif );
if (p != NULL)
{
if (netif->input( p, netif) != ERR_OK )
{
pbuf_free(p);
}if (netif->input( p, netif) != ERR_OK) { ... }
}if (p != NULL) { ... }
...} while(p!=NULL);
}{ ... }
/* ... */
err_t ethernetif_init(struct netif *netif)
{
LWIP_ASSERT("netif != NULL", (netif != NULL));
#if LWIP_NETIF_HOSTNAME
netif->hostname = "lwip";/* ... */
#endif
netif->name[0] = IFNAME0;
netif->name[1] = IFNAME1;
/* ... */
netif->output = etharp_output;
netif->linkoutput = low_level_output;
low_level_init(netif);
return ERR_OK;
}{ ... }
/* ... */
void pbuf_free_custom(struct pbuf *p)
{
struct pbuf_custom* custom_pbuf = (struct pbuf_custom*)p;
LWIP_MEMPOOL_FREE(RX_POOL, custom_pbuf);
/* ... */
if (RxAllocStatus == RX_ALLOC_ERROR)
{
RxAllocStatus = RX_ALLOC_OK;
}if (RxAllocStatus == RX_ALLOC_ERROR) { ... }
}{ ... }
/* ... */
u32_t sys_now(void)
{
return HAL_GetTick();
}{ ... }
/* ... */
/* ... */
void HAL_ETH_MspInit(ETH_HandleTypeDef *heth)
{
GPIO_InitTypeDef GPIO_InitStructure = {0};
__HAL_RCC_GPIOA_CLK_ENABLE();
__HAL_RCC_GPIOB_CLK_ENABLE();
__HAL_RCC_GPIOC_CLK_ENABLE();
__HAL_RCC_GPIOE_CLK_ENABLE();
__HAL_RCC_GPIOF_CLK_ENABLE();
__HAL_RCC_GPIOG_CLK_ENABLE();
__HAL_RCC_GPIOH_CLK_ENABLE();
__HAL_RCC_GPIOI_CLK_ENABLE();
/* ... */
GPIO_InitStructure.Speed = GPIO_SPEED_HIGH;
GPIO_InitStructure.Mode = GPIO_MODE_AF_PP;
GPIO_InitStructure.Pull = GPIO_NOPULL;
GPIO_InitStructure.Alternate = GPIO_AF11_ETH;
GPIO_InitStructure.Pin = GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_7;
HAL_GPIO_Init(GPIOA, &GPIO_InitStructure);
GPIO_InitStructure.Pin = GPIO_PIN_5;
HAL_GPIO_Init(GPIOB, &GPIO_InitStructure);
GPIO_InitStructure.Pin = GPIO_PIN_2;
HAL_GPIO_Init(GPIOE, &GPIO_InitStructure);
GPIO_InitStructure.Pin = GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_3 | GPIO_PIN_4 | GPIO_PIN_5;
HAL_GPIO_Init(GPIOC, &GPIO_InitStructure);
GPIO_InitStructure.Pin = GPIO_PIN_11 | GPIO_PIN_13 | GPIO_PIN_14;
HAL_GPIO_Init(GPIOG, &GPIO_InitStructure);
GPIO_InitStructure.Pin = GPIO_PIN_6 | GPIO_PIN_7;
HAL_GPIO_Init(GPIOH, &GPIO_InitStructure);
/* ... */
/* ... */
/* ... */
__HAL_RCC_ETH_CLK_ENABLE();
}{ ... }
/* ... */
/* ... */
int32_t ETH_PHY_IO_Init(void)
{
/* ... */
HAL_ETH_SetMDIOClockRange(&EthHandle);
return 0;
}{ ... }
/* ... */
int32_t ETH_PHY_IO_DeInit (void)
{
return 0;
}{ ... }
/* ... */
int32_t ETH_PHY_IO_ReadReg(uint32_t DevAddr, uint32_t RegAddr, uint32_t *pRegVal)
{
if(HAL_ETH_ReadPHYRegister(&EthHandle, DevAddr, RegAddr, pRegVal) != HAL_OK)
{
return -1;
}if (HAL_ETH_ReadPHYRegister(&EthHandle, DevAddr, RegAddr, pRegVal) != HAL_OK) { ... }
return 0;
}{ ... }
/* ... */
int32_t ETH_PHY_IO_WriteReg(uint32_t DevAddr, uint32_t RegAddr, uint32_t RegVal)
{
if(HAL_ETH_WritePHYRegister(&EthHandle, DevAddr, RegAddr, RegVal) != HAL_OK)
{
return -1;
}if (HAL_ETH_WritePHYRegister(&EthHandle, DevAddr, RegAddr, RegVal) != HAL_OK) { ... }
return 0;
}{ ... }
/* ... */
int32_t ETH_PHY_IO_GetTick(void)
{
return HAL_GetTick();
}{ ... }
/* ... */
void ethernet_link_check_state(struct netif *netif)
{
ETH_MACConfigTypeDef MACConf = {0};
int32_t PHYLinkState = 0U;
uint32_t linkchanged = 0U, speed = 0U, duplex =0U;
PHYLinkState = DP83848_GetLinkState(&DP83848);
if(netif_is_link_up(netif) && (PHYLinkState <= DP83848_STATUS_LINK_DOWN))
{
HAL_ETH_Stop(&EthHandle);
netif_set_down(netif);
netif_set_link_down(netif);
}if (netif_is_link_up(netif) && (PHYLinkState <= DP83848_STATUS_LINK_DOWN)) { ... }
else if(!netif_is_link_up(netif) && (PHYLinkState > DP83848_STATUS_LINK_DOWN))
{
switch (PHYLinkState)
{
case DP83848_STATUS_100MBITS_FULLDUPLEX:
duplex = ETH_FULLDUPLEX_MODE;
speed = ETH_SPEED_100M;
linkchanged = 1;
break;case DP83848_STATUS_100MBITS_FULLDUPLEX:
case DP83848_STATUS_100MBITS_HALFDUPLEX:
duplex = ETH_HALFDUPLEX_MODE;
speed = ETH_SPEED_100M;
linkchanged = 1;
break;case DP83848_STATUS_100MBITS_HALFDUPLEX:
case DP83848_STATUS_10MBITS_FULLDUPLEX:
duplex = ETH_FULLDUPLEX_MODE;
speed = ETH_SPEED_10M;
linkchanged = 1;
break;case DP83848_STATUS_10MBITS_FULLDUPLEX:
case DP83848_STATUS_10MBITS_HALFDUPLEX:
duplex = ETH_HALFDUPLEX_MODE;
speed = ETH_SPEED_10M;
linkchanged = 1;
break;case DP83848_STATUS_10MBITS_HALFDUPLEX:
default:
break;default
}switch (PHYLinkState) { ... }
if(linkchanged)
{
HAL_ETH_GetMACConfig(&EthHandle, &MACConf);
MACConf.DuplexMode = duplex;
MACConf.Speed = speed;
HAL_ETH_SetMACConfig(&EthHandle, &MACConf);
HAL_ETH_Start(&EthHandle);
netif_set_up(netif);
netif_set_link_up(netif);
}if (linkchanged) { ... }
}else if (!netif_is_link_up(netif) && (PHYLinkState > DP83848_STATUS_LINK_DOWN)) { ... }
}{ ... }
void HAL_ETH_RxAllocateCallback(uint8_t **buff)
{
struct pbuf_custom *p = LWIP_MEMPOOL_ALLOC(RX_POOL);
if (p)
{
*buff = (uint8_t *)p + offsetof(RxBuff_t, buff);
p->custom_free_function = pbuf_free_custom;
/* ... */
pbuf_alloced_custom(PBUF_RAW, 0, PBUF_REF, p, *buff, ETH_RX_BUF_SIZE);
}if (p) { ... }
else
{
RxAllocStatus = RX_ALLOC_ERROR;
*buff = NULL;
}else { ... }
}{ ... }
void HAL_ETH_RxLinkCallback(void **pStart, void **pEnd, uint8_t *buff, uint16_t Length)
{
struct pbuf **ppStart = (struct pbuf **)pStart;
struct pbuf **ppEnd = (struct pbuf **)pEnd;
struct pbuf *p = NULL;
p = (struct pbuf *)(buff - offsetof(RxBuff_t, buff));
p->next = NULL;
p->tot_len = 0;
p->len = Length;
if (!*ppStart)
{
*ppStart = p;
}if (!*ppStart) { ... }
else
{
(*ppEnd)->next = p;
}else { ... }
*ppEnd = p;
/* ... */
for (p = *ppStart; p != NULL; p = p->next)
{
p->tot_len += Length;
}for (p = *ppStart; p != NULL; p = p->next) { ... }
}{ ... }
void HAL_ETH_TxFreeCallback(uint32_t * buff)
{
pbuf_free((struct pbuf *)buff);
}{ ... }