/**************************************************************************//* *//* Copyright (c) Microsoft Corporation. All rights reserved. *//* *//* This software is licensed under the Microsoft Software License *//* Terms for Microsoft Azure RTOS. Full text of the license can be *//* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA *//* and in the root directory of this software. *//* */.../**************************************************************************/.../**************************************************************************//**************************************************************************//** *//** ThreadX Component *//** *//** Port Specific *//** */.../**************************************************************************//**************************************************************************/.../**************************************************************************//* *//* PORT SPECIFIC C INFORMATION RELEASE *//* *//* tx_port.h Cortex-M4/GNU *//* 6.1.10 *//* *//* AUTHOR *//* *//* Scott Larson, Microsoft Corporation *//* *//* DESCRIPTION *//* *//* This file contains data type definitions that make the ThreadX *//* real-time kernel function identically on a variety of different *//* processor architectures. For example, the size or number of bits *//* in an "int" data type vary between microprocessor architectures and *//* even C compilers for the same microprocessor. ThreadX does not *//* directly use native C data types. Instead, ThreadX creates its *//* own special types that can be mapped to actual data types by this *//* file to guarantee consistency in the interface and functionality. *//* *//* This file replaces the previous Cortex-M3/M4/M7 files. It unifies *//* the ARMv7-M architecture and compilers into one common file. *//* *//* RELEASE HISTORY *//* *//* DATE NAME DESCRIPTION *//* *//* 06-02-2021 Scott Larson Initial Version 6.1.7 *//* 01-31-2022 Scott Larson Modified comments, updated *//* typedef to fix misra *//* violation, *//* fixed predefined macro, *//* resulting in version 6.1.10 *//* */.../**************************************************************************/#ifndefTX_PORT_H#defineTX_PORT_H/* Determine if the optional ThreadX user define file should be used. */#ifdefTX_INCLUDE_USER_DEFINE_FILE/* Yes, include the user defines in tx_user.h. The defines in this file may alternately be defined on the command line. *//* ... */#include"tx_user.h"/* ... */#endif/* Define compiler library include files. */#include<stdlib.h>#include<string.h>#ifdef__ICCARM__#include<intrinsics.h>/* IAR Intrinsics */#define__asm____asm/* Define to make all inline asm look similar */#ifdefTX_ENABLE_IAR_LIBRARY_SUPPORT#include<yvals.h>#endif/* ... */#endif/* __ICCARM__ */#ifdef__ghs__#include<arm_ghs.h>#include"tx_ghs.h"/* ... */#endif/* __ghs__ */#if!defined(__GNUC__)&&!defined(__CC_ARM)#define__get_control_value__get_CONTROL#define__set_control_value__set_CONTROL/* ... */#endif#ifndef__GNUC__#define__get_ipsr_value__get_IPSR#endif/* Define ThreadX basic types for this port. */#defineVOIDvoidtypedefcharCHAR;typedefunsignedcharUCHAR;typedefintINT;typedefunsignedintUINT;typedeflongLONG;typedefunsignedlongULONG;typedefunsignedlonglongULONG64;typedefshortSHORT;typedefunsignedshortUSHORT;#defineULONG64_DEFINED/* Define the priority levels for ThreadX. Legal values range from 32 to 1024 and MUST be evenly divisible by 32. *//* ... */#ifndefTX_MAX_PRIORITIES#defineTX_MAX_PRIORITIES32#endif/* Define the minimum stack for a ThreadX thread on this processor. If the size supplied during thread creation is less than this value, the thread create call will return an error. *//* ... */#ifndefTX_MINIMUM_STACK#defineTX_MINIMUM_STACK200/* Minimum stack size for this port */#endif/* Define the system timer thread's default stack size and priority. These are only applicable if TX_TIMER_PROCESS_IN_ISR is not defined. *//* ... */#ifndefTX_TIMER_THREAD_STACK_SIZE#defineTX_TIMER_THREAD_STACK_SIZE1024/* Default timer thread stack size */#endif#ifndefTX_TIMER_THREAD_PRIORITY#defineTX_TIMER_THREAD_PRIORITY0/* Default timer thread priority */#endif/* Define various constants for the ThreadX Cortex-M port. */#defineTX_INT_DISABLE1/* Disable interrupts */#defineTX_INT_ENABLE0/* Enable interrupts *//* Define the clock source for trace event entry time stamp. The following two item are port specific. For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock source constants would be:#define TX_TRACE_TIME_SOURCE *((ULONG *) 0x0a800024)#define TX_TRACE_TIME_MASK 0x0000FFFFUL*//* ... */#ifndefTX_MISRA_ENABLE#ifndefTX_TRACE_TIME_SOURCE#defineTX_TRACE_TIME_SOURCE*((ULONG*)0xE0001004)#endif/* ... */#elseULONG_tx_misra_time_stamp_get(VOID);#defineTX_TRACE_TIME_SOURCE_tx_misra_time_stamp_get()/* ... */#endif#ifndefTX_TRACE_TIME_MASK#defineTX_TRACE_TIME_MASK0xFFFFFFFFUL#endif#ifdef__ghs__/* Define constants for Green Hills EventAnalyzer. *//* Define the number of ticks per second. This informs the EventAnalyzer what the timestamps represent. By default, this is set to 1,000,000 i.e., one tick every microsecond. *//* ... */#defineTX_EL_TICKS_PER_SECOND1000000/* Define the method of how to get the upper and lower 32-bits of the time stamp. By default, simply simulate the time-stamp source with a counter. *//* ... */#defineread_tbu()_tx_el_time_base_upper#defineread_tbl()++_tx_el_time_base_lower/* ... */#endif/* __ghs__ *//* Define the port specific options for the _tx_build_options variable. This variable indicates how the ThreadX library was built. *//* ... */#defineTX_PORT_SPECIFIC_BUILD_OPTIONS(0)/* Define the in-line initialization constant so that modules with in-line initialization capabilities can prevent their initialization from being a function call. *//* ... */#ifdefTX_MISRA_ENABLE#defineTX_DISABLE_INLINE#else#defineTX_INLINE_INITIALIZATION#endif/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is disabled. When the following is defined, ThreadX thread stack checking is enabled. If stack checking is enabled (TX_ENABLE_STACK_CHECKING is defined), the TX_DISABLE_STACK_FILLING define is negated, thereby forcing the stack fill which is necessary for the stack checking logic. *//* ... */#ifndefTX_MISRA_ENABLE#ifdefTX_ENABLE_STACK_CHECKING#undefTX_DISABLE_STACK_FILLING#endif/* ... */#endif/* Define the TX_THREAD control block extensions for this port. The main reason for the multiple macros is so that backward compatibility can be maintained with existing ThreadX kernel awareness modules. *//* ... */#defineTX_THREAD_EXTENSION_0#defineTX_THREAD_EXTENSION_1#ifdefTX_ENABLE_IAR_LIBRARY_SUPPORT#defineTX_THREAD_EXTENSION_2VOID*tx_thread_iar_tls_pointer;#elifdefined(__ghs__)#defineTX_THREAD_EXTENSION_2VOID*tx_thread_eh_globals;\intErrno;/* errno. */\char*strtok_saved_pos;/* strtok() position. */.../* ... */#else#defineTX_THREAD_EXTENSION_2#endif#defineTX_THREAD_EXTENSION_3/* Define the port extensions of the remaining ThreadX objects. */#defineTX_BLOCK_POOL_EXTENSION#defineTX_BYTE_POOL_EXTENSION#defineTX_EVENT_FLAGS_GROUP_EXTENSION#defineTX_MUTEX_EXTENSION#defineTX_QUEUE_EXTENSION#defineTX_SEMAPHORE_EXTENSION#defineTX_TIMER_EXTENSION8 defines/* Define the user extension field of the thread control block. Nothing additional is needed for this port so it is defined as white space. *//* ... */#ifndefTX_THREAD_USER_EXTENSION#defineTX_THREAD_USER_EXTENSION#endif/* Define the macros for processing extensions in tx_thread_create, tx_thread_delete, tx_thread_shell_entry, and tx_thread_terminate. *//* ... */#ifdefTX_ENABLE_IAR_LIBRARY_SUPPORT#if(__VER__<8000000)#defineTX_THREAD_CREATE_EXTENSION(thread_ptr)thread_ptr->tx_thread_iar_tls_pointer=__iar_dlib_perthread_allocate();#defineTX_THREAD_DELETE_EXTENSION(thread_ptr)__iar_dlib_perthread_deallocate(thread_ptr->tx_thread_iar_tls_pointer);\thread_ptr->tx_thread_iar_tls_pointer=TX_NULL;...#defineTX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION__iar_dlib_perthread_access(0);/* ... */#elsevoid*_tx_iar_create_per_thread_tls_area(void);void_tx_iar_destroy_per_thread_tls_area(void*tls_ptr);void__iar_Initlocks(void);#defineTX_THREAD_CREATE_EXTENSION(thread_ptr)thread_ptr->tx_thread_iar_tls_pointer=_tx_iar_create_per_thread_tls_area();#defineTX_THREAD_DELETE_EXTENSION(thread_ptr)do{_tx_iar_destroy_per_thread_tls_area(thread_ptr->tx_thread_iar_tls_pointer);\thread_ptr->tx_thread_iar_tls_pointer=TX_NULL;...}while(0);...#defineTX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATIONdo{__iar_Initlocks();}while(0);/* ... */#endif/* ... */#else#defineTX_THREAD_CREATE_EXTENSION(thread_ptr)#defineTX_THREAD_DELETE_EXTENSION(thread_ptr)/* ... */#endif#ifdefined(__ARMVFP__)||defined(__ARM_PCS_VFP)||defined(__ARM_FP)||defined(__TARGET_FPU_VFP)||defined(__VFP__)#ifdefTX_MISRA_ENABLEULONG_tx_misra_control_get(void);void_tx_misra_control_set(ULONGvalue);ULONG_tx_misra_fpccr_get(void);void_tx_misra_vfp_touch(void);/* ... */#else/* TX_MISRA_ENABLE not defined *//* Define some helper functions (these are intrinsics in some compilers). */#ifdef__GNUC__/* GCC and ARM Compiler 6 */__attribute__((always_inline))staticinlineULONG__get_control_value(void){ULONGcontrol_value;__asm__volatile(" MRS %0,CONTROL ":"=r"(control_value));return(control_value);}{ ... }__attribute__((always_inline))staticinlinevoid__set_control_value(ULONGcontrol_value){__asm__volatile(" MSR CONTROL,%0"::"r"(control_value):"memory");}{ ... }#defineTX_VFP_TOUCH()__asm__volatile("VMOV.F32 s0, s0");/* ... */#elifdefined(__CC_ARM)/* ARM Compiler 5 */__attribute__((always_inline))ULONG__get_control_value(void){ULONGcontrol_value;__asmvolatile("MRS control_value,CONTROL");return(control_value);}__get_control_value (void) { ... }__attribute__((always_inline))void__set_control_value(ULONGcontrol_value){__asm__volatile("MSR CONTROL,control_value");}__set_control_value (ULONG control_value) { ... }/* Can't access VFP registers with inline asm, so define this in tx_thread_schedule. */void_tx_vfp_access(void);#defineTX_VFP_TOUCH()_tx_vfp_access();/* ... */#elifdefined(__ICCARM__)/* IAR */#defineTX_VFP_TOUCH()__asm__volatile("VMOV.F32 s0, s0");#endif/* Helper functions for different compilers *//* ... */#endif/* TX_MISRA_ENABLE *//* A completed thread falls into _thread_shell_entry and we can simply deactivate the FPU via CONTROL.FPCA in order to ensure no lazy stacking will occur. *//* ... */#ifndefTX_MISRA_ENABLE#defineTX_THREAD_COMPLETED_EXTENSION(thread_ptr){\ULONG_tx_vfp_state;\_tx_vfp_state=__get_control_value();\_tx_vfp_state=_tx_vfp_state&~((ULONG)0x4);\__set_control_value(_tx_vfp_state);\...}.../* ... */#else#defineTX_THREAD_COMPLETED_EXTENSION(thread_ptr){\ULONG_tx_vfp_state;\_tx_vfp_state=_tx_misra_control_get();\_tx_vfp_state=_tx_vfp_state&~((ULONG)0x4);\_tx_misra_control_set(_tx_vfp_state);\...}.../* ... */#endif/* A thread can be terminated by another thread, so we first check if it's self-terminating and not in an ISR. If so, deactivate the FPU via CONTROL.FPCA. Otherwise we are in an interrupt or another thread is terminating this one, so if the FPCCR.LSPACT bit is set, we need to save the CONTROL.FPCA state, touch the FPU to flush the lazy FPU save, then restore the CONTROL.FPCA state. *//* ... */#ifndefTX_MISRA_ENABLE#defineTX_THREAD_TERMINATED_EXTENSION(thread_ptr){\ULONG_tx_system_state;\_tx_system_state=TX_THREAD_GET_SYSTEM_STATE();\if((_tx_system_state==((ULONG)0))&&((thread_ptr)==_tx_thread_current_ptr))\{\ULONG_tx_vfp_state;\_tx_vfp_state=__get_control_value();\_tx_vfp_state=_tx_vfp_state&~((ULONG)0x4);\__set_control_value(_tx_vfp_state);\...}\else\{\ULONG_tx_fpccr;\_tx_fpccr=*((ULONG*)0xE000EF34);\_tx_fpccr=_tx_fpccr&((ULONG)0x01);\if(_tx_fpccr==((ULONG)0x01))\{\ULONG_tx_vfp_state;\_tx_vfp_state=__get_control_value();\_tx_vfp_state=_tx_vfp_state&((ULONG)0x4);\TX_VFP_TOUCH();\if(_tx_vfp_state==((ULONG)0))\{\_tx_vfp_state=__get_control_value();\_tx_vfp_state=_tx_vfp_state&~((ULONG)0x4);\__set_control_value(_tx_vfp_state);\...}\...}\...}\...}.../* ... */#else#defineTX_THREAD_TERMINATED_EXTENSION(thread_ptr){\ULONG_tx_system_state;\_tx_system_state=TX_THREAD_GET_SYSTEM_STATE();\if((_tx_system_state==((ULONG)0))&&((thread_ptr)==_tx_thread_current_ptr))\{\ULONG_tx_vfp_state;\_tx_vfp_state=_tx_misra_control_get();\_tx_vfp_state=_tx_vfp_state&~((ULONG)0x4);\_tx_misra_control_set(_tx_vfp_state);\...}\else\{\ULONG_tx_fpccr;\_tx_fpccr=_tx_misra_fpccr_get();\_tx_fpccr=_tx_fpccr&((ULONG)0x01);\if(_tx_fpccr==((ULONG)0x01))\{\ULONG_tx_vfp_state;\_tx_vfp_state=_tx_misra_control_get();\_tx_vfp_state=_tx_vfp_state&((ULONG)0x4);\_tx_misra_vfp_touch();\if(_tx_vfp_state==((ULONG)0))\{\_tx_vfp_state=_tx_misra_control_get();\_tx_vfp_state=_tx_vfp_state&~((ULONG)0x4);\_tx_misra_control_set(_tx_vfp_state);\...}\...}\...}\...}.../* ... */#endif/* ... */#else/* No VFP in use */#defineTX_THREAD_COMPLETED_EXTENSION(thread_ptr)#defineTX_THREAD_TERMINATED_EXTENSION(thread_ptr)/* ... */#endif/* defined(__ARMVFP__) || defined(__ARM_PCS_VFP) || defined(__ARM_FP) || defined(__TARGET_FPU_VFP) || defined(__VFP__) *//* Define the ThreadX object creation extensions for the remaining objects. */#defineTX_BLOCK_POOL_CREATE_EXTENSION(pool_ptr)#defineTX_BYTE_POOL_CREATE_EXTENSION(pool_ptr)#defineTX_EVENT_FLAGS_GROUP_CREATE_EXTENSION(group_ptr)#defineTX_MUTEX_CREATE_EXTENSION(mutex_ptr)#defineTX_QUEUE_CREATE_EXTENSION(queue_ptr)#defineTX_SEMAPHORE_CREATE_EXTENSION(semaphore_ptr)#defineTX_TIMER_CREATE_EXTENSION(timer_ptr)/* Define the ThreadX object deletion extensions for the remaining objects. */#defineTX_BLOCK_POOL_DELETE_EXTENSION(pool_ptr)#defineTX_BYTE_POOL_DELETE_EXTENSION(pool_ptr)#defineTX_EVENT_FLAGS_GROUP_DELETE_EXTENSION(group_ptr)#defineTX_MUTEX_DELETE_EXTENSION(mutex_ptr)#defineTX_QUEUE_DELETE_EXTENSION(queue_ptr)#defineTX_SEMAPHORE_DELETE_EXTENSION(semaphore_ptr)#defineTX_TIMER_DELETE_EXTENSION(timer_ptr)14 defines/* Define the get system state macro. */#ifndefTX_THREAD_GET_SYSTEM_STATE#ifndefTX_MISRA_ENABLE#ifdef__CC_ARM/* ARM Compiler 5 */registerunsignedint_ipsr__asm("ipsr");#defineTX_THREAD_GET_SYSTEM_STATE()(_tx_thread_system_state|_ipsr)/* ... */#elifdefined(__GNUC__)/* GCC and ARM Compiler 6 */__attribute__((always_inline))staticinlineunsignedint__get_ipsr_value(void){unsignedintipsr_value;__asm__volatile(" MRS %0,IPSR ":"=r"(ipsr_value));return(ipsr_value);}{ ... }#defineTX_THREAD_GET_SYSTEM_STATE()(_tx_thread_system_state|__get_ipsr_value())/* ... */#elifdefined(__ICCARM__)/* IAR */#defineTX_THREAD_GET_SYSTEM_STATE()(_tx_thread_system_state|__get_IPSR())/* ... */#endif/* TX_THREAD_GET_SYSTEM_STATE for different compilers *//* ... */#else/* TX_MISRA_ENABLE is defined, use MISRA function. */ULONG_tx_misra_ipsr_get(VOID);#defineTX_THREAD_GET_SYSTEM_STATE()(_tx_thread_system_state|_tx_misra_ipsr_get())/* ... */#endif/* TX_MISRA_ENABLE *//* ... */#endif/* TX_THREAD_GET_SYSTEM_STATE *//* Define the check for whether or not to call the _tx_thread_system_return function. A non-zero value indicates that _tx_thread_system_return should not be called. This overrides the definition in tx_thread.h for Cortex-M since so we don't waste time checking the _tx_thread_system_state variable that is always zero after initialization for Cortex-M ports. *//* ... */#ifndefTX_THREAD_SYSTEM_RETURN_CHECK#defineTX_THREAD_SYSTEM_RETURN_CHECK(c)(c)=((ULONG)_tx_thread_preempt_disable);#endif/* Define the macro to ensure _tx_thread_preempt_disable is set early in initialization in order to prevent early scheduling on Cortex-M parts. *//* ... */#defineTX_PORT_SPECIFIC_POST_INITIALIZATION_tx_thread_preempt_disable++;#ifndefTX_DISABLE_INLINE/* Define the TX_LOWEST_SET_BIT_CALCULATE macro for each compiler. */#ifdef__ICCARM__/* IAR Compiler */#defineTX_LOWEST_SET_BIT_CALCULATE(m,b)(b)=(UINT)__CLZ(__RBIT((m)));#elifdefined(__CC_ARM)/* AC5 Compiler */#defineTX_LOWEST_SET_BIT_CALCULATE(m,b)(b)=(UINT)__clz(__rbit((m)));#elifdefined(__GNUC__)/* GCC and AC6 Compiler */#defineTX_LOWEST_SET_BIT_CALCULATE(m,b)__asm__volatile(" RBIT %0,%1 ":"=r"(m):"r"(m));\__asm__volatile(" CLZ %0,%1 ":"=r"(b):"r"(m));.../* ... */#endif/* Define the interrupt disable/restore macros for each compiler. */#ifdefined(__GNUC__)||defined(__ICCARM__)/*** GCC/AC6 and IAR ***/__attribute__((always_inline))staticinlineunsignedint__get_interrupt_posture(void){unsignedintposture;#ifdefTX_PORT_USE_BASEPRI__asm__volatile("MRS %0, BASEPRI ":"=r"(posture));#else__asm__volatile("MRS %0, PRIMASK ":"=r"(posture));#endifreturn(posture);}{ ... }#ifdefTX_PORT_USE_BASEPRI__attribute__((always_inline))staticinlinevoid__set_basepri_value(unsignedintbasepri_value){__asm__volatile("MSR BASEPRI,%0 "::"r"(basepri_value));}__set_basepri_value (unsigned int basepri_value) { ... }/* ... */#else__attribute__((always_inline))staticinlinevoid__enable_interrupts(void){__asm__volatile("CPSIE i":::"memory");}{ ... }/* ... */#endif__attribute__((always_inline))staticinlinevoid__restore_interrupt(unsignedintint_posture){#ifdefTX_PORT_USE_BASEPRI__set_basepri_value(int_posture);//__asm__ volatile ("MSR BASEPRI,%0": : "r" (int_posture): "memory");/* ... */#else__asm__volatile("MSR PRIMASK,%0"::"r"(int_posture):"memory");#endif}{ ... }__attribute__((always_inline))staticinlineunsignedint__disable_interrupts(void){unsignedintint_posture;int_posture=__get_interrupt_posture();#ifdefTX_PORT_USE_BASEPRI__set_basepri_value(TX_PORT_BASEPRI);#else__asm__volatile("CPSID i":::"memory");#endifreturn(int_posture);}{ ... }__attribute__((always_inline))staticinlinevoid_tx_thread_system_return_inline(void){unsignedintinterrupt_save;/* Set PendSV to invoke ThreadX scheduler. */*((ULONG*)0xE000ED04)=((ULONG)0x10000000);if(__get_ipsr_value()==0){interrupt_save=__get_interrupt_posture();#ifdefTX_PORT_USE_BASEPRI__set_basepri_value(0);#else__enable_interrupts();#endif__restore_interrupt(interrupt_save);}if (__get_ipsr_value() == 0) { ... }}{ ... }#defineTX_INTERRUPT_SAVE_AREAUINTinterrupt_save;#defineTX_DISABLEinterrupt_save=__disable_interrupts();#defineTX_RESTORE__restore_interrupt(interrupt_save);/*** End GCC/AC6 and IAR ***//* ... */#elifdefined(__CC_ARM)/*** AC5 ***/static__inlineunsignedint__get_interrupt_posture(void){unsignedintposture;#ifdefTX_PORT_USE_BASEPRI__asm__volatile("MRS #posture, BASEPRI");#else__asm__volatile("MRS #posture, PRIMASK");#endifreturn(posture);}__get_interrupt_posture (void) { ... }#ifdefTX_PORT_USE_BASEPRIstatic__inlinevoid__set_basepri_value(unsignedintbasepri_value){__asm__volatile("MSR BASEPRI, #basepri_value");}__set_basepri_value (unsigned int basepri_value) { ... }/* ... */#endifstatic__inlineunsignedint__disable_interrupts(void){unsignedintint_posture;int_posture=__get_interrupt_posture();#ifdefTX_PORT_USE_BASEPRI__set_basepri_value(TX_PORT_BASEPRI);#else__asm__volatile("CPSID i");#endifreturn(int_posture);}__disable_interrupts (void) { ... }static__inlinevoid__restore_interrupt(unsignedintint_posture){#ifdefTX_PORT_USE_BASEPRI__set_basepri_value(int_posture);#else__asm__volatile("MSR PRIMASK, #int_posture");#endif}__restore_interrupt (unsigned int int_posture) { ... }staticvoid_tx_thread_system_return_inline(void){unsignedintinterrupt_save;/* Set PendSV to invoke ThreadX scheduler. */*((ULONG*)0xE000ED04)=((ULONG)0x10000000);if(_ipsr==0){#ifdefTX_PORT_USE_BASEPRIinterrupt_save=__get_interrupt_posture();__set_basepri_value(0);__set_basepri_value(interrupt_save);/* ... */#elseinterrupt_save=__disable_irq();__enable_irq();if(interrupt_save!=0)__disable_irq();/* ... */#endif}if (_ipsr == 0) { ... }}_tx_thread_system_return_inline (void) { ... }#defineTX_INTERRUPT_SAVE_AREAUINTinterrupt_save;#defineTX_DISABLEinterrupt_save=__disable_interrupts();#defineTX_RESTORE__restore_interrupt(interrupt_save);/*** End AC5 ***//* ... */#endif/* Interrupt disable/restore macros for each compiler. *//* Redefine _tx_thread_system_return for improved performance. */#define_tx_thread_system_return_tx_thread_system_return_inline/* ... */#else/* TX_DISABLE_INLINE is defined */UINT_tx_thread_interrupt_disable(VOID);VOID_tx_thread_interrupt_restore(UINTprevious_posture);#defineTX_INTERRUPT_SAVE_AREAregisterUINTinterrupt_save;#defineTX_DISABLEinterrupt_save=_tx_thread_interrupt_disable();#defineTX_RESTORE_tx_thread_interrupt_restore(interrupt_save);/* ... */#endif/* TX_DISABLE_INLINE *//* Define FPU extension for the Cortex-M. Each is assumed to be called in the context of the executing thread. These are no longer needed, but are preserved for backward compatibility only. *//* ... */voidtx_thread_fpu_enable(void);voidtx_thread_fpu_disable(void);/* Define the version ID of ThreadX. This may be utilized by the application. */#ifdefTX_THREAD_INITCHAR_tx_version_id[]="Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M4/GNU Version 6.1.9 *";/* ... */#else#ifdefTX_MISRA_ENABLEexternCHAR_tx_version_id[100];#elseexternCHAR_tx_version_id[];#endif/* ... */#endif/* ... */...#endif