FSMC_NORSRAM_TimingTypeDef::CLKDivision field

Defines the period of CLK clock output signal, expressed in number of HCLK cycles. This parameter can be a value between Min_Data = 2 and Max_Data = 16.

Syntax

from stm32f4xx_ll_fsmc.h:259

uint32_t CLKDivision;

Examples

FSMC_NORSRAM_TimingTypeDef::CLKDivision is referenced by 7 libraries and example projects.

References

Location	Referrer	Text
stm32f4xx_ll_fsmc.h:259		uint32_t CLKDivision; /*!< Defines the period of CLK clock output signal, expressed in number of
stm32f4xx_ll_fsmc.c:392	FSMC_NORSRAM_Timing_Init()	assert_param(IS_FSMC_CLK_DIV(Timing->CLKDivision));
stm32f4xx_ll_fsmc.c:402	FSMC_NORSRAM_Timing_Init()	(((Timing->CLKDivision) - 1U) << FSMC_BTR1_CLKDIV_Pos) \|
stm32f4xx_ll_fsmc.c:411	FSMC_NORSRAM_Timing_Init()	tmpr \|= (uint32_t)(((Timing->CLKDivision) - 1U) << FSMC_BTR1_CLKDIV_Pos);

Data Use

Functions reading FSMC_NORSRAM_TimingTypeDef::CLKDivision

FSMC_NORSRAM_TimingTypeDef::CLKDivision

FSMC_NORSRAM_Timing_Init()

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Type of FSMC_NORSRAM_TimingTypeDef::CLKDivision

FSMC_NORSRAM_TimingTypeDef::CLKDivision

uint32_t

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