HAL + 0/7 examples
CodeScope will show references to FSMC_NORSRAM_InitTypeDef::NSBank from the following samples and libraries:
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STM324xG_EVAL
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CodeScopeSTM32 Libraries and SamplesHALFSMC_NORSRAM_InitTypeDef::NSBank

FSMC_NORSRAM_InitTypeDef::NSBank field

Specifies the NORSRAM memory device that will be used. This parameter can be a value of FSMC_NORSRAM_Bank

Syntax

uint32_t NSBank;

Examples

FSMC_NORSRAM_InitTypeDef::NSBank is referenced by 7 libraries and example projects.

References

LocationReferrerText
stm32f4xx_ll_fsmc.h:168
uint32_t NSBank; /*!< Specifies the NORSRAM memory device that will be used.
stm32f4xx_hal_nor.c:269HAL_NOR_Init()
(void)FMC_NORSRAM_Timing_Init(hnor->Instance, Timing, hnor->Init.NSBank);
stm32f4xx_hal_nor.c:273HAL_NOR_Init()
hnor->Init.NSBank, hnor->Init.ExtendedMode);
stm32f4xx_hal_nor.c:276HAL_NOR_Init()
__FMC_NORSRAM_ENABLE(hnor->Instance, hnor->Init.NSBank);
stm32f4xx_hal_nor.c:292HAL_NOR_Init()
if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
stm32f4xx_hal_nor.c:296HAL_NOR_Init()
else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
stm32f4xx_hal_nor.c:300HAL_NOR_Init()
else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
stm32f4xx_hal_nor.c:311HAL_NOR_Init()
(void)FMC_NORSRAM_WriteOperation_Disable(hnor->Instance, hnor->Init.NSBank);
stm32f4xx_hal_nor.c:359HAL_NOR_DeInit()
(void)FMC_NORSRAM_DeInit(hnor->Instance, hnor->Extended, hnor->Init.NSBank);
stm32f4xx_hal_nor.c:470HAL_NOR_Read_ID()
if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
stm32f4xx_hal_nor.c:474HAL_NOR_Read_ID()
else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
stm32f4xx_hal_nor.c:478HAL_NOR_Read_ID()
else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
stm32f4xx_hal_nor.c:574HAL_NOR_ReturnToReadMode()
if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
stm32f4xx_hal_nor.c:578HAL_NOR_ReturnToReadMode()
else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
stm32f4xx_hal_nor.c:582HAL_NOR_ReturnToReadMode()
else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
stm32f4xx_hal_nor.c:652HAL_NOR_Read()
if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
stm32f4xx_hal_nor.c:656HAL_NOR_Read()
else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
stm32f4xx_hal_nor.c:660HAL_NOR_Read()
else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
stm32f4xx_hal_nor.c:746HAL_NOR_Program()
if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
stm32f4xx_hal_nor.c:750HAL_NOR_Program()
else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
stm32f4xx_hal_nor.c:754HAL_NOR_Program()
else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
stm32f4xx_hal_nor.c:850HAL_NOR_ReadBuffer()
if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
stm32f4xx_hal_nor.c:854HAL_NOR_ReadBuffer()
else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
stm32f4xx_hal_nor.c:858HAL_NOR_ReadBuffer()
else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
stm32f4xx_hal_nor.c:955HAL_NOR_ProgramBuffer()
if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
stm32f4xx_hal_nor.c:959HAL_NOR_ProgramBuffer()
else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
stm32f4xx_hal_nor.c:963HAL_NOR_ProgramBuffer()
else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
stm32f4xx_hal_nor.c:1071HAL_NOR_Erase_Block()
if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
stm32f4xx_hal_nor.c:1075HAL_NOR_Erase_Block()
else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
stm32f4xx_hal_nor.c:1079HAL_NOR_Erase_Block()
else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
stm32f4xx_hal_nor.c:1168HAL_NOR_Erase_Chip()
if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
stm32f4xx_hal_nor.c:1172HAL_NOR_Erase_Chip()
else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
stm32f4xx_hal_nor.c:1176HAL_NOR_Erase_Chip()
else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
stm32f4xx_hal_nor.c:1262HAL_NOR_Read_CFI()
if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
stm32f4xx_hal_nor.c:1266HAL_NOR_Read_CFI()
else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
stm32f4xx_hal_nor.c:1270HAL_NOR_Read_CFI()
else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
stm32f4xx_hal_nor.c:1437HAL_NOR_WriteOperation_Enable()
(void)FMC_NORSRAM_WriteOperation_Enable(hnor->Instance, hnor->Init.NSBank);
stm32f4xx_hal_nor.c:1471HAL_NOR_WriteOperation_Disable()
(void)FMC_NORSRAM_WriteOperation_Disable(hnor->Instance, hnor->Init.NSBank);
stm32f4xx_hal_sram.c:208HAL_SRAM_Init()
(void)FMC_NORSRAM_Timing_Init(hsram->Instance, Timing, hsram->Init.NSBank);
stm32f4xx_hal_sram.c:211HAL_SRAM_Init()
(void)FMC_NORSRAM_Extended_Timing_Init(hsram->Extended, ExtTiming, hsram->Init.NSBank,
stm32f4xx_hal_sram.c:215HAL_SRAM_Init()
__FMC_NORSRAM_ENABLE(hsram->Instance, hsram->Init.NSBank);
stm32f4xx_hal_sram.c:245HAL_SRAM_DeInit()
(void)FMC_NORSRAM_DeInit(hsram->Instance, hsram->Extended, hsram->Init.NSBank);
stm32f4xx_hal_sram.c:942HAL_SRAM_WriteOperation_Enable()
(void)FMC_NORSRAM_WriteOperation_Enable(hsram->Instance, hsram->Init.NSBank);
stm32f4xx_hal_sram.c:976HAL_SRAM_WriteOperation_Disable()
(void)FMC_NORSRAM_WriteOperation_Disable(hsram->Instance, hsram->Init.NSBank);
stm32f4xx_ll_fsmc.c:229FSMC_NORSRAM_Init()
assert_param(IS_FSMC_NORSRAM_BANK(Init->NSBank));
stm32f4xx_ll_fsmc.c:253FSMC_NORSRAM_Init()
__FSMC_NORSRAM_DISABLE(Device, Init->NSBank);
stm32f4xx_ll_fsmc.c:314FSMC_NORSRAM_Init()
MODIFY_REG(Device->BTCR[Init->NSBank], mask, btcr_reg);
stm32f4xx_ll_fsmc.c:318FSMC_NORSRAM_Init()
if ((Init->ContinuousClock == FSMC_CONTINUOUS_CLOCK_SYNC_ASYNC) && (Init->NSBank != FSMC_NORSRAM_BANK1))
stm32f4xx_ll_fsmc.c:325FSMC_NORSRAM_Init()
if (Init->NSBank != FSMC_NORSRAM_BANK1)

Data Use

Type of FSMC_NORSRAM_InitTypeDef::NSBank
FSMC_NORSRAM_InitTypeDef::NSBank
uint32_t
all items filtered out