Location | Referrer | Text |
---|---|---|
stm32f4xx_hal_can.h:218 | ||
stm32f4xx_hal_can.c:335 | HAL_CAN_Init() | SET_BIT(hcan->Instance->MCR, CAN_MCR_INRQ); |
stm32f4xx_hal_can.c:341 | HAL_CAN_Init() | while ((hcan->Instance->MSR & CAN_MSR_INAK) == 0U) |
stm32f4xx_hal_can.c:356 | HAL_CAN_Init() | CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_SLEEP); |
stm32f4xx_hal_can.c:362 | HAL_CAN_Init() | while ((hcan->Instance->MSR & CAN_MSR_SLAK) != 0U) |
stm32f4xx_hal_can.c:379 | HAL_CAN_Init() | SET_BIT(hcan->Instance->MCR, CAN_MCR_TTCM); |
stm32f4xx_hal_can.c:383 | HAL_CAN_Init() | CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_TTCM); |
stm32f4xx_hal_can.c:389 | HAL_CAN_Init() | SET_BIT(hcan->Instance->MCR, CAN_MCR_ABOM); |
stm32f4xx_hal_can.c:393 | HAL_CAN_Init() | CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_ABOM); |
stm32f4xx_hal_can.c:399 | HAL_CAN_Init() | SET_BIT(hcan->Instance->MCR, CAN_MCR_AWUM); |
stm32f4xx_hal_can.c:403 | HAL_CAN_Init() | CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_AWUM); |
stm32f4xx_hal_can.c:409 | HAL_CAN_Init() | CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_NART); |
stm32f4xx_hal_can.c:413 | HAL_CAN_Init() | SET_BIT(hcan->Instance->MCR, CAN_MCR_NART); |
stm32f4xx_hal_can.c:419 | HAL_CAN_Init() | SET_BIT(hcan->Instance->MCR, CAN_MCR_RFLM); |
stm32f4xx_hal_can.c:423 | HAL_CAN_Init() | CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_RFLM); |
stm32f4xx_hal_can.c:429 | HAL_CAN_Init() | SET_BIT(hcan->Instance->MCR, CAN_MCR_TXFP); |
stm32f4xx_hal_can.c:433 | HAL_CAN_Init() | CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_TXFP); |
stm32f4xx_hal_can.c:437 | HAL_CAN_Init() | WRITE_REG(hcan->Instance->BTR, (uint32_t)(hcan->Init.Mode | |
stm32f4xx_hal_can.c:489 | HAL_CAN_DeInit() | SET_BIT(hcan->Instance->MCR, CAN_MCR_RESET); |
stm32f4xx_hal_can.c:843 | HAL_CAN_ConfigFilter() | CAN_TypeDef *can_ip = hcan->Instance; |
stm32f4xx_hal_can.c:861 | HAL_CAN_ConfigFilter() | if (hcan->Instance == CAN3) |
stm32f4xx_hal_can.c:1044 | HAL_CAN_Start() | CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_INRQ); |
stm32f4xx_hal_can.c:1050 | HAL_CAN_Start() | while ((hcan->Instance->MSR & CAN_MSR_INAK) != 0U) |
stm32f4xx_hal_can.c:1093 | HAL_CAN_Stop() | SET_BIT(hcan->Instance->MCR, CAN_MCR_INRQ); |
stm32f4xx_hal_can.c:1099 | HAL_CAN_Stop() | while ((hcan->Instance->MSR & CAN_MSR_INAK) == 0U) |
stm32f4xx_hal_can.c:1115 | HAL_CAN_Stop() | CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_SLEEP); |
stm32f4xx_hal_can.c:1149 | HAL_CAN_RequestSleep() | SET_BIT(hcan->Instance->MCR, CAN_MCR_SLEEP); |
stm32f4xx_hal_can.c:1181 | HAL_CAN_WakeUp() | CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_SLEEP); |
stm32f4xx_hal_can.c:1197 | HAL_CAN_WakeUp() | } while ((hcan->Instance->MSR & CAN_MSR_SLAK) != 0U); |
stm32f4xx_hal_can.c:1228 | HAL_CAN_IsSleepActive() | if ((hcan->Instance->MSR & CAN_MSR_SLAK) != 0U) |
stm32f4xx_hal_can.c:1255 | HAL_CAN_AddTxMessage() | uint32_t tsr = READ_REG(hcan->Instance->TSR); |
stm32f4xx_hal_can.c:1288 | HAL_CAN_AddTxMessage() | hcan->Instance->sTxMailBox[transmitmailbox].TIR = ((pHeader->StdId << CAN_TI0R_STID_Pos) | |
stm32f4xx_hal_can.c:1293 | HAL_CAN_AddTxMessage() | hcan->Instance->sTxMailBox[transmitmailbox].TIR = ((pHeader->ExtId << CAN_TI0R_EXID_Pos) | |
stm32f4xx_hal_can.c:1299 | HAL_CAN_AddTxMessage() | hcan->Instance->sTxMailBox[transmitmailbox].TDTR = (pHeader->DLC); |
stm32f4xx_hal_can.c:1304 | HAL_CAN_AddTxMessage() | SET_BIT(hcan->Instance->sTxMailBox[transmitmailbox].TDTR, CAN_TDT0R_TGT); |
stm32f4xx_hal_can.c:1308 | HAL_CAN_AddTxMessage() | WRITE_REG(hcan->Instance->sTxMailBox[transmitmailbox].TDHR, |
stm32f4xx_hal_can.c:1313 | HAL_CAN_AddTxMessage() | WRITE_REG(hcan->Instance->sTxMailBox[transmitmailbox].TDLR, |
stm32f4xx_hal_can.c:1320 | HAL_CAN_AddTxMessage() | SET_BIT(hcan->Instance->sTxMailBox[transmitmailbox].TIR, CAN_TI0R_TXRQ); |
stm32f4xx_hal_can.c:1364 | HAL_CAN_AbortTxRequest() | SET_BIT(hcan->Instance->TSR, CAN_TSR_ABRQ0); |
stm32f4xx_hal_can.c:1371 | HAL_CAN_AbortTxRequest() | SET_BIT(hcan->Instance->TSR, CAN_TSR_ABRQ1); |
stm32f4xx_hal_can.c:1378 | HAL_CAN_AbortTxRequest() | SET_BIT(hcan->Instance->TSR, CAN_TSR_ABRQ2); |
stm32f4xx_hal_can.c:1408 | HAL_CAN_GetTxMailboxesFreeLevel() | if ((hcan->Instance->TSR & CAN_TSR_TME0) != 0U) |
stm32f4xx_hal_can.c:1414 | HAL_CAN_GetTxMailboxesFreeLevel() | if ((hcan->Instance->TSR & CAN_TSR_TME1) != 0U) |
stm32f4xx_hal_can.c:1420 | HAL_CAN_GetTxMailboxesFreeLevel() | if ((hcan->Instance->TSR & CAN_TSR_TME2) != 0U) |
stm32f4xx_hal_can.c:1454 | HAL_CAN_IsTxMessagePending() | if ((hcan->Instance->TSR & (TxMailboxes << CAN_TSR_TME0_Pos)) != (TxMailboxes << CAN_TSR_TME0_Pos)) |
stm32f4xx_hal_can.c:1490 | HAL_CAN_GetTxTimestamp() | timestamp = (hcan->Instance->sTxMailBox[transmitmailbox].TDTR & CAN_TDT0R_TIME) >> CAN_TDT0R_TIME_Pos; |
stm32f4xx_hal_can.c:1522 | HAL_CAN_GetRxMessage() | if ((hcan->Instance->RF0R & CAN_RF0R_FMP0) == 0U) |
stm32f4xx_hal_can.c:1533 | HAL_CAN_GetRxMessage() | if ((hcan->Instance->RF1R & CAN_RF1R_FMP1) == 0U) |
stm32f4xx_hal_can.c:1543 | HAL_CAN_GetRxMessage() | pHeader->IDE = CAN_RI0R_IDE & hcan->Instance->sFIFOMailBox[RxFifo].RIR; |
stm32f4xx_hal_can.c:1546 | HAL_CAN_GetRxMessage() | pHeader->StdId = (CAN_RI0R_STID & hcan->Instance->sFIFOMailBox[RxFifo].RIR) >> CAN_TI0R_STID_Pos; |
stm32f4xx_hal_can.c:1551 | HAL_CAN_GetRxMessage() | hcan->Instance->sFIFOMailBox[RxFifo].RIR) >> CAN_RI0R_EXID_Pos; |
stm32f4xx_hal_can.c:1553 | HAL_CAN_GetRxMessage() | pHeader->RTR = (CAN_RI0R_RTR & hcan->Instance->sFIFOMailBox[RxFifo].RIR); |
stm32f4xx_hal_can.c:1554 | HAL_CAN_GetRxMessage() | if (((CAN_RDT0R_DLC & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_DLC_Pos) >= 8U) |
stm32f4xx_hal_can.c:1561 | HAL_CAN_GetRxMessage() | pHeader->DLC = (CAN_RDT0R_DLC & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_DLC_Pos; |
stm32f4xx_hal_can.c:1563 | HAL_CAN_GetRxMessage() | pHeader->FilterMatchIndex = (CAN_RDT0R_FMI & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_FMI_Pos; |
stm32f4xx_hal_can.c:1564 | HAL_CAN_GetRxMessage() | pHeader->Timestamp = (CAN_RDT0R_TIME & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_TIME_Pos; |
stm32f4xx_hal_can.c:1567 | HAL_CAN_GetRxMessage() | aData[0] = (uint8_t)((CAN_RDL0R_DATA0 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA0_Pos); |
stm32f4xx_hal_can.c:1568 | HAL_CAN_GetRxMessage() | aData[1] = (uint8_t)((CAN_RDL0R_DATA1 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA1_Pos); |
stm32f4xx_hal_can.c:1569 | HAL_CAN_GetRxMessage() | aData[2] = (uint8_t)((CAN_RDL0R_DATA2 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA2_Pos); |
stm32f4xx_hal_can.c:1570 | HAL_CAN_GetRxMessage() | aData[3] = (uint8_t)((CAN_RDL0R_DATA3 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA3_Pos); |
stm32f4xx_hal_can.c:1571 | HAL_CAN_GetRxMessage() | aData[4] = (uint8_t)((CAN_RDH0R_DATA4 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA4_Pos); |
stm32f4xx_hal_can.c:1572 | HAL_CAN_GetRxMessage() | aData[5] = (uint8_t)((CAN_RDH0R_DATA5 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA5_Pos); |
stm32f4xx_hal_can.c:1573 | HAL_CAN_GetRxMessage() | aData[6] = (uint8_t)((CAN_RDH0R_DATA6 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA6_Pos); |
stm32f4xx_hal_can.c:1574 | HAL_CAN_GetRxMessage() | aData[7] = (uint8_t)((CAN_RDH0R_DATA7 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA7_Pos); |
stm32f4xx_hal_can.c:1580 | HAL_CAN_GetRxMessage() | SET_BIT(hcan->Instance->RF0R, CAN_RF0R_RFOM0); |
stm32f4xx_hal_can.c:1585 | HAL_CAN_GetRxMessage() | SET_BIT(hcan->Instance->RF1R, CAN_RF1R_RFOM1); |
stm32f4xx_hal_can.c:1621 | HAL_CAN_GetRxFifoFillLevel() | filllevel = hcan->Instance->RF0R & CAN_RF0R_FMP0; |
stm32f4xx_hal_can.c:1625 | HAL_CAN_GetRxFifoFillLevel() | filllevel = hcan->Instance->RF1R & CAN_RF1R_FMP1; |
stm32f4xx_hal_can.c:1672 | HAL_CAN_ActivateNotification() | __HAL_CAN_ENABLE_IT(hcan, ActiveITs); |
stm32f4xx_hal_can.c:1705 | HAL_CAN_DeactivateNotification() | __HAL_CAN_DISABLE_IT(hcan, InactiveITs); |
stm32f4xx_hal_can.c:1728 | HAL_CAN_IRQHandler() | uint32_t interrupts = READ_REG(hcan->Instance->IER); |
stm32f4xx_hal_can.c:1729 | HAL_CAN_IRQHandler() | uint32_t msrflags = READ_REG(hcan->Instance->MSR); |
stm32f4xx_hal_can.c:1730 | HAL_CAN_IRQHandler() | uint32_t tsrflags = READ_REG(hcan->Instance->TSR); |
stm32f4xx_hal_can.c:1731 | HAL_CAN_IRQHandler() | uint32_t rf0rflags = READ_REG(hcan->Instance->RF0R); |
stm32f4xx_hal_can.c:1732 | HAL_CAN_IRQHandler() | uint32_t rf1rflags = READ_REG(hcan->Instance->RF1R); |
stm32f4xx_hal_can.c:1733 | HAL_CAN_IRQHandler() | uint32_t esrflags = READ_REG(hcan->Instance->ESR); |
stm32f4xx_hal_can.c:1742 | HAL_CAN_IRQHandler() | __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_RQCP0); |
stm32f4xx_hal_can.c:1785 | HAL_CAN_IRQHandler() | __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_RQCP1); |
stm32f4xx_hal_can.c:1828 | HAL_CAN_IRQHandler() | __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_RQCP2); |
stm32f4xx_hal_can.c:1877 | HAL_CAN_IRQHandler() | __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FOV0); |
stm32f4xx_hal_can.c:1887 | HAL_CAN_IRQHandler() | __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FF0); |
stm32f4xx_hal_can.c:1904 | HAL_CAN_IRQHandler() | if ((hcan->Instance->RF0R & CAN_RF0R_FMP0) != 0U) |
stm32f4xx_hal_can.c:1926 | HAL_CAN_IRQHandler() | __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FOV1); |
stm32f4xx_hal_can.c:1936 | HAL_CAN_IRQHandler() | __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FF1); |
stm32f4xx_hal_can.c:1953 | HAL_CAN_IRQHandler() | if ((hcan->Instance->RF1R & CAN_RF1R_FMP1) != 0U) |
stm32f4xx_hal_can.c:1972 | HAL_CAN_IRQHandler() | __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_SLAKI); |
stm32f4xx_hal_can.c:1991 | HAL_CAN_IRQHandler() | __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_WKU); |
stm32f4xx_hal_can.c:2074 | HAL_CAN_IRQHandler() | CLEAR_BIT(hcan->Instance->ESR, CAN_ESR_LEC); |
stm32f4xx_hal_can.c:2079 | HAL_CAN_IRQHandler() | __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_ERRI); |
stm32f4xx_hal_can.c:2384 | HAL_CAN_GetState() | if ((hcan->Instance->MSR & CAN_MSR_SLAK) != 0U) |
stm32f4xx_hal_can.c:2390 | HAL_CAN_GetState() | else if ((hcan->Instance->MCR & CAN_MCR_SLEEP) != 0U) |