LL_LPTIM_CLK_FILTER_4 macro

External clock signal level change must be stable for at least 4 clock periods before it is considered as valid transition

Syntax

#define LL_LPTIM_CLK_FILTER_4 LPTIM_CFGR_CKFLT_1

Location	Text
stm32f4xx_ll_lptim.h:239	#define LL_LPTIM_CLK_FILTER_4 LPTIM_CFGR_CKFLT_1 /!<External clock signal level change must be stable for at least 4 clock periods before it is considered as valid transition/