1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
273
274
275
276
277
278
279
280
281
282
285
286
293
294
295
296
299
302
303
306
307
308
311
312
313
314
315
317
318
321
322
323
326
327
328
329
330
331
332
333
334
335
336
337
338
341
342
343
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
367
368
369
370
373
374
375
376
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
402
408
409
410
414
415
416
426
427
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
493
494
495
505
506
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
575
576
577
578
581
582
583
584
588
589
590
591
592
593
594
600
606
607
608
612
613
614
615
616
617
618
619
620
624
625
626
627
632
633
634
635
636
637
638
639
640
641
642
643
647
648
649
650
651
652
653
654
655
659
660
661
662
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
686
694
695
700
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
734
735
736
737
738
739
740
743
746
749
752
756
757
758
774
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
807
810
813
816
820
821
822
838
843
844
845
846
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
894
895
896
897
898
902
906
907
908
909
910
911
912
913
925
926
927
928
929
930
931
932
933
945
946
947
952
953
954
955
956
957
963
964
965
966
967
968
969
970
971
972
973
974
975
976
981
982
983
984
985
986
990
994
995
996
997
998
999
1000
1001
1002
1014
1015
1016
1017
1018
1019
1020
1021
1022
1023
1024
1025
1037
1038
1039
1040
1041
1042
1043
1044
1045
1046
1051
1052
1053
1054
1055
1056
1057
1058
1059
1060
1061
1062
1063
1068
1069
1070
1071
1072
1073
1077
1081
1082
1083
1084
1085
1086
1087
1088
1089
1090
1096
1097
1098
1099
1100
1101
1102
1103
1104
1105
1106
1107
1108
1109
1110
1111
1112
1113
1114
1115
1116
1117
1118
1119
1120
1121
1122
1123
1124
1129
1130
1131
1132
1133
1134
1138
1142
1143
1144
1145
1146
1147
1148
1149
1150
1151
1152
1153
1154
1155
1161
1162
1163
1164
1165
1166
1167
1168
1169
1170
1171
1172
1173
1174
1175
1176
1177
1178
1179
1180
1181
1182
1183
1184
1190
1191
1192
1193
1194
1195
1196
1197
1198
1199
1200
1201
1202
1203
1204
1205
1206
1207
1212
1220
1221
1227
1228
1229
1230
1231
1232
1233
1234
1235
1236
1237
1238
1239
1244
1245
1246
1247
1248
1249
1253
1257
1258
1259
1260
1261
1262
1263
1264
1265
1266
1267
1268
1269
1270
1271
1272
1273
1274
1275
1276
1277
1278
1279
1280
1281
1282
1283
1284
1285
1286
1287
1288
1289
1290
1291
1292
1293
1294
1295
1296
1297
1298
1299
1300
1301
1302
1303
1304
1305
1306
1307
1312
1313
1314
1315
1316
1317
1318
1319
1320
1321
1322
1323
1324
1325
1326
1332
1333
1334
1335
1336
1337
1338
1339
1340
1341
1342
1343
1344
1345
1350
1351
1352
1353
1354
1355
1356
1357
1361
1365
1366
1367
1368
1369
1370
1382
1383
1384
1385
1386
1387
1388
1389
1390
1391
1403
1404
1405
1406
1407
1408
1409
1410
1411
1412
1413
1418
1419
1420
1421
1422
1423
1424
1425
1426
1427
1428
1429
1430
1435
1436
1437
1438
1439
1440
1441
1442
1443
1444
1455
1456
1457
1458
1459
1460
1461
1462
1463
1464
1465
1466
1467
1468
1469
1470
1471
1472
1473
1474
1475
1476
1477
1478
1479
1480
1481
1482
1483
1484
1485
1486
1487
1488
1493
1494
1495
1496
1507
1508
1510
1511
1512
1513
1514
1515
1516
1517
1518
1519
1520
1521
1522
1523
1524
1529
1537
1538
1544
1545
1546
1547
1548
1549
1550
1551
1552
1553
1554
1555
1556
1561
1562
1563
1564
1565
1566
1567
1568
1569
1570
1574
1578
1579
1580
1581
1582
1583
1584
1588
1589
1590
1591
1592
1593
1594
1599
1603
1604
1605
1606
1607
1608
1609
1610
1611
1612
1613
1614
1615
1616
1617
1618
1619
1620
1621
1626
1632
1633
1634
1635
1636
1639
1640
1641
1642
1643
1644
1645
1646
1647
1648
1649
1650
1651
1652
1653
1658
1663
1664
1667
1668
1669
1670
1671
1672
1673
1674
1675
1676
1677
1678
1679
1680
1681
1682
1688
1689
1690
1691
1695
1696
1697
1698
1699
1700
1701
1702
1703
1704
1705
1706
1707
1708
1709
1715
1716
1717
1718
1719
1720
1721
1722
1723
1724
1725
1726
1727
1728
1729
1730
1731
1732
1733
1734
1735
1736
1737
1738
1739
1740
1744
1745
1746
1748
1749
1750
1751
1752
1756
1760
1761
1765
1769
1770
1771
1772
1778
1779
1783
1787
1788
1792
1796
1797
1798
1799
1800
1801
1802
1803
1804
1805
1806
1807
1808
1809
1810
1811
1812
1813
1814
1815
1816
1817
1818
1823
1824
1825
1826
1830
1831
1832
1833
1834
1835
1836
1837
1838
1839
1844
1845
1846
1847
1848
1849
1850
1851
1852
1853
1854
1859
1867
1868
1873
1881
1882
1883
1884
1885
1886
1887
1888
1889
1890
1891
1892
1893
1894
1895
1896
1897
1898
1899
1900
1901
1902
1903
1904
1905
1906
1907
1908
1909
1910
1911
1912
1913
1914
1915
1916
1917
1918
1921
1924
1927
1930
1933
1936
1939
1945
1946
1947
1965
1966
1967
1968
1969
1970
1971
1972
1973
1974
1975
1976
1977
1978
1979
1980
1981
1982
1983
1984
1985
1986
1987
1988
1989
1990
1991
1992
1993
1994
1995
1996
1997
1998
1999
2000
2003
2006
2009
2012
2015
2018
2021
2027
2028
2029
2047
2048
2049
2050
2051
2052
2053
2054
2055
2056
2057
2058
2059
2060
2061
2062
2063
2064
2065
2066
2067
2068
2069
2070
2071
2072
2073
2074
2075
2076
2077
2078
2082
2083
2084
2085
2086
2087
2088
2089
2090
2091
2092
2093
2099
2100
2101
2102
2103
2107
2108
2109
2110
2111
2112
2113
2114
2115
2116
2117
2120
2121
2122
2123
2124
2125
2126
2127
2128
2129
2130
2131
2132
2133
2134
2135
2136
2137
2138
2139
2140
2141
2142
2143
2144
2145
2146
2147
2148
2149
2150
2151
2152
2153
2154
2155
2156
2157
2158
2159
2160
2161
2162
2167
2171
2172
2173
2174
2178
2179
2180
2181
2182
2183
2184
2185
2186
2187
2188
2189
2190
2191
2192
2193
2194
2195
2196
2197
2198
2199
2200
2201
2202
2203
2204
2205
2206
2207
2208
2209
2210
2211
2215
2216
2217
2218
2219
2222
2223
2224
2225
2226
2227
2228
2229
2230
2231
2232
2233
2234
2235
2236
2237
2238
2239
2240
2241
2242
2243
2244
2245
2246
2247
2248
2249
2250
2251
2252
2253
2254
2255
2256
2257
2258
2259
2260
2261
2262
2263
2264
2265
2266
2267
2268
2274
2278
2279
2280
2281
2282
2283
2284
2285
2286
2287
2288
2289
2290
2291
2292
2293
2294
2295
2296
2297
2298
2304
2305
2306
2307
2308
2309
2310
2322
2323
2324
2325
2326
2327
2328
2329
2330
2331
2332
2333
2334
2335
2336
2337
2343
2344
2345
2346
2347
2348
2354
2355
2356
2357
2358
2359
2360
2361
2362
2368
2373
2374
2375
2376
2377
2378
2379
2380
2381
2382
2383
2384
2385
2386
2387
2388
2389
2390
2391
2392
2393
2394
2395
2396
2397
2398
2399
2400
2401
2405
2406
2407
2408
2409
2415
2416
2417
2418
2419
2420
2421
2422
2423
2429
2430
2431
2432
2433
2434
2435
2436
2437
2438
2439
2440
2441
2442
2443
2444
2445
2446
2447
2448
2449
2450
2451
2452
2453
2454
2455
2456
2457
2458
2459
2460
2461
2462
2463
2467
2468
2472
2473
2474
2475
2476
2477
2478
2479
2480
2486
2487
2488
2489
2490
2491
2492
2493
2494
2495
2496
2497
2498
2499
2500
2501
2502
2503
2504
2509
2510
2514
2515
2516
2517
2518
2519
2520
2521
2522
2523
2524
2525
2526
2527
2528
2529
2530
2531
2532
2533
2534
2535
2536
2537
2538
2539
2540
2544
2545
2549
2550
2551
2552
2553
2554
2555
2556
2557
2563
2564
2565
2566
2567
2568
2569
2570
2571
2572
2573
2574
2575
2576
2577
2578
2579
2580
2581
2586
2587
2591
2592
2593
2594
2595
2601
2602
2603
2604
2605
2606
2607
2608
2609
2615
2630
2631
2632
2633
2634
2640
2641
2642
2643
2644
2645
2646
2647
2648
2649
2650
2651
2652
2653
2654
2655
2656
2657
2658
2659
2660
2661
2662
2663
2664
2665
2666
2667
2668
2669
2670
2671
2672
2673
2674
2675
2676
2682
2686
2687
2688
2689
2690
2691
2692
2693
2694
2695
2696
2697
2698
2699
2700
2701
2702
2703
2704
2705
2706
2712
2713
2714
2715
2716
2717
2718
2730
2731
2732
2733
2734
2735
2736
2737
2738
2739
2740
2741
2742
2743
2744
2745
2746
2747
2748
2749
2750
2755
2756
2757
2758
2759
2760
2761
2762
2763
2764
2765
2766
2772
2773
2774
2775
2776
2777
2778
2779
2780
2786
2791
2792
2793
2794
2795
2796
2797
2798
2799
2800
2801
2802
2803
2804
2805
2806
2807
2808
2809
2810
2811
2812
2813
2814
2815
2816
2817
2818
2819
2823
2824
2825
2826
2827
2833
2834
2835
2836
2837
2838
2839
2840
2841
2847
2848
2849
2850
2851
2852
2853
2854
2855
2856
2857
2858
2859
2860
2861
2862
2863
2864
2865
2866
2867
2868
2869
2870
2871
2872
2873
2874
2875
2876
2877
2878
2879
2880
2881
2885
2886
2890
2891
2897
2902
2903
2904
2905
2906
2907
2908
2909
2910
2911
2912
2913
2914
2915
2916
2917
2918
2919
2920
2925
2926
2930
2931
2932
2933
2934
2935
2936
2937
2938
2939
2940
2941
2942
2943
2944
2945
2946
2947
2948
2949
2950
2951
2952
2953
2954
2955
2956
2960
2961
2965
2966
2972
2977
2978
2979
2980
2981
2982
2983
2984
2985
2986
2987
2988
2989
2990
2991
2992
2993
2994
2995
3000
3001
3005
3006
3007
3008
3009
3015
3016
3017
3018
3019
3020
3021
3022
3023
3029
3044
3045
3046
3047
3048
3054
3055
3056
3057
3058
3059
3060
3061
3062
3063
3064
3065
3066
3067
3068
3069
3070
3071
3072
3073
3074
3075
3081
3082
3083
3084
3085
3086
3087
3088
3089
3090
3091
3092
3093
3094
3095
3096
3102
3103
3104
3105
3106
3107
3108
3109
3110
3111
3112
3113
3114
3115
3116
3117
3118
3119
3120
3121
3122
3123
3124
3125
3130
3131
3132
3133
3134
3135
3136
3137
3138
3144
3145
3146
3147
3148
3149
3150
3151
3152
3153
3154
3155
3156
3157
3158
3159
3160
3161
3162
3163
3164
3165
3166
3167
3168
3169
3170
3171
3172
3173
3174
3175
3176
3177
3178
3179
3180
3186
3192
3193
3194
3195
3196
3201
3202
3203
3204
3205
3206
3207
3208
3209
3210
3211
3217
3218
3219
3220
3221
3222
3223
3224
3225
3226
3227
3228
3229
3230
3231
3232
3233
3234
3235
3236
3237
3238
3239
3240
3241
3242
3243
3244
3245
3246
3247
3248
3249
3250
3251
3252
3253
3254
3255
3256
3257
3258
3259
3260
3261
3262
3263
3264
3265
3266
3267
3268
3269
3270
3271
3272
3273
3274
3275
3276
3277
3278
3279
3280
3281
3282
3283
3284
3285
3286
3287
3288
3294
3295
3296
3297
3298
3299
3300
3301
3302
3303
3304
3305
3306
3307
3308
3309
3310
3311
3312
3317
3318
3319
3320
3321
3322
3323
3324
3325
3326
3327
3328
3329
3330
3331
3332
3333
3334
3335
3336
3337
3338
3339
3340
3341
3342
3343
3344
3345
3346
3347
3348
3349
3350
3351
3352
3353
3354
3355
3356
3357
3358
3359
3360
3361
3362
3363
3364
3365
3366
3367
3368
3369
3370
3371
3372
3373
3374
3375
3376
3377
3378
3379
3380
3381
3382
3383
3384
3385
3386
3387
3388
3389
3390
3391
3392
3393
3394
3395
3396
3397
3398
3399
3400
3401
3402
3403
3404
3405
3406
3407
3408
3409
3410
3411
3412
3413
3414
3415
3416
3417
3421
3426
3427
3428
3429
3430
3431
3432
3433
3434
3435
3436
3437
3438
3439
3440
3441
3442
3443
3444
3445
3446
3447
3448
3449
3450
3451
3452
3453
3454
3455
3456
3457
3458
3459
3460
3461
3462
3463
3464
3465
3466
3467
3468
3469
3470
3471
3472
3473
3474
3475
3476
3477
3478
3479
3480
3481
3482
3483
3484
3485
3486
3487
3488
3489
3490
3491
3492
3493
3494
3495
3496
3497
3498
3499
3500
3501
3502
3503
3504
3505
3506
3507
3508
3509
3510
3511
3512
3513
3514
3515
3516
3521
3522
3523
3524
3525
3526
3527
3528
3529
3530
3531
3532
3533
3534
3535
3536
3537
3538
3539
3540
3541
3542
3543
3548
3549
3550
3551
3552
3553
3554
3555
3556
3557
3558
3559
3560
3561
3562
3563
3564
3565
3566
3567
3568
3569
3577
3578
3583
3591
3592
3593
3594
3595
3596
3597
3598
3599
3607
3608
3613
3621
3622
3623
3624
3625
3626
3627
3628
3629
3630
3631
3632
3633
3634
3635
3636
3637
3640
3641
3642
3647
3655
3656
3659
3660
3661
3662
3663
3664
3665
3666
3667
3668
3669
3670
3671
3672
3673
3674
3679
3684
3685
3690
3694
3695
3698
3699
3700
3701
3702
3703
3704
3705
3706
3707
3708
3709
3710
3711
3712
3713
3714
3715
3716
3717
3718
3719
3720
3721
3722
3723
3724
3725
3726
3727
3733
3734
3735
3736
3737
3738
3739
3740
3741
3742
3743
3744
3745
3746
3747
3748
3749
3750
3751
3752
3753
3754
3755
3756
3757
3758
3762
3766
3767
3768
3769
3770
3771
3772
3773
3774
3775
3776
3777
3778
3779
3780
3781
3782
3783
3784
3785
3786
3787
3788
3789
3790
3791
3792
3793
3794
3795
3796
3797
3798
3799
3800
3801
3802
3803
3804
3805
3806
3815
3819
3820
3821
3822
3823
3824
3825
3826
3827
3828
3829
3830
3831
3832
3833
3834
3835
3836
3837
3838
3839
3848
3852
3853
3854
3855
3856
3857
3858
3859
3860
3861
3862
3863
3864
3865
3866
3867
3868
3869
3870
3871
3872
3880
3884
3885
3886
3887
3888
3889
3890
3891
3892
3893
3894
3895
3896
3897
3898
3899
3900
3901
3902
3903
3911
3915
3916
3917
3918
3924
3925
3926
3927
3928
3929
3930
3931
3932
3933
3934
3935
3936
3942
3943
3944
3945
3946
3947
3948
3949
3950
3951
3952
3953
3954
3955
3956
3957
3958
3959
3960
3961
3962
3963
3964
3965
3966
3967
3968
3969
3970
3971
3972
3973
3974
3975
3976
3977
3978
3979
3980
3984
3988
3992
4000
4004
4005
4011
4012
4013
4014
4015
4016
4017
4018
4019
4020
4021
4022
4023
4024
4025
4026
4027
4028
4029
4030
4031
4032
4033
4034
4035
4036
4037
4038
4039
4040
4041
4042
4043
4044
4045
4046
4047
4048
4049
4050
4051
4052
4055
4058
4059
4060
4061
4064
4065
4070
4071
4072
4073
4074
4075
4076
4077
4078
4079
4080
4081
4082
4083
4088
4089
4090
4091
4092
4093
4094
4095
4096
4097
4098
4099
4100
4101
4106
4107
4108
4109
4110
4111
4112
4113
4114
4115
4116
4117
4118
4119
4124
4125
4126
4127
4128
4129
4130
4131
4132
4133
4134
4135
4136
4137
4142
4143
4144
4145
4146
4147
4148
4149
4150
4151
4152
4153
4154
4155
4156
4157
4158
4163
4164
4165
4166
4167
4168
4169
4170
4178
4179
4180
4181
4186
4187
4188
4189
4190
4191
4192
4193
4194
4195
4196
4200
4204
4208
4212
4216
4220
4224
4225
4226
4227
4228
4229
4230
4234
4238
4242
4243
4244
4245
4246
4247
4252
4253
4254
4255
4260
4261
4262
4263
4264
4265
4266
4267
4268
4269
4270
4271
4272
4273
4274
4278
4279
4280
4281
4282
4283
4284
4285
4286
4287
4288
4293
4294
4295
4296
4297
4298
4299
4303
4304
4305
4306
4307
4308
4309
4310
4314
4315
4316
4317
4318
4319
4320
4321
4322
4323
4324
4329
4330
4331
4332
4337
4338
4339
4340
4341
4342
4347
4352
4353
4354
4355
4356
4357
4362
4363
4364
4365
4366
4367
4368
4373
4374
4375
4376
4377
4378
4379
4383
4388
4389
4393
4394
4395
4396
4397
4402
4403
4404
4405
4406
4407
4408
4409
4410
4411
4414
4415
4416
4419
4420
4421
/* ... */
#include "stm32f4xx_hal.h"
/* ... */
#ifdef HAL_DFSDM_MODULE_ENABLED
#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
/* ... */
/* ... */
#define DFSDM_FLTCR1_MSB_RCH_OFFSET 8U
#define DFSDM_MSB_MASK 0xFFFF0000U
#define DFSDM_LSB_MASK 0x0000FFFFU
#define DFSDM_CKAB_TIMEOUT 5000U
#define DFSDM1_CHANNEL_NUMBER 4U
5 defines#if defined (DFSDM2_Channel0)
#define DFSDM2_CHANNEL_NUMBER 8U
#endif
/* ... */
/* ... */
/* ... */
Private define
/* ... */
__IO uint32_t v_dfsdm1ChannelCounter = 0U;
DFSDM_Channel_HandleTypeDef* a_dfsdm1ChannelHandle[DFSDM1_CHANNEL_NUMBER] = {NULL};
#if defined (DFSDM2_Channel0)
__IO uint32_t v_dfsdm2ChannelCounter = 0U;
DFSDM_Channel_HandleTypeDef* a_dfsdm2ChannelHandle[DFSDM2_CHANNEL_NUMBER] = {NULL};/* ... */
#endif
/* ... */
Private variables
/* ... */
static uint32_t DFSDM_GetInjChannelsNbr(uint32_t Channels);
static uint32_t DFSDM_GetChannelFromInstance(const DFSDM_Channel_TypeDef *Instance);
static void DFSDM_RegConvStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
static void DFSDM_RegConvStop(DFSDM_Filter_HandleTypeDef* hdfsdm_filter);
static void DFSDM_InjConvStart(DFSDM_Filter_HandleTypeDef* hdfsdm_filter);
static void DFSDM_InjConvStop(DFSDM_Filter_HandleTypeDef* hdfsdm_filter);
static void DFSDM_DMARegularHalfConvCplt(DMA_HandleTypeDef *hdma);
static void DFSDM_DMARegularConvCplt(DMA_HandleTypeDef *hdma);
static void DFSDM_DMAInjectedHalfConvCplt(DMA_HandleTypeDef *hdma);
static void DFSDM_DMAInjectedConvCplt(DMA_HandleTypeDef *hdma);
static void DFSDM_DMAError(DMA_HandleTypeDef *hdma);
/* ... */
Private function prototypes
/* ... */
/* ... */
/* ... */
HAL_StatusTypeDef HAL_DFSDM_ChannelInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
{
#if defined(DFSDM2_Channel0)
__IO uint32_t* channelCounterPtr;
DFSDM_Channel_HandleTypeDef **channelHandleTable;
DFSDM_Channel_TypeDef* channel0Instance;/* ... */
#endif
if(hdfsdm_channel == NULL)
{
return HAL_ERROR;
}if (hdfsdm_channel == NULL) { ... }
assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance));
assert_param(IS_FUNCTIONAL_STATE(hdfsdm_channel->Init.OutputClock.Activation));
assert_param(IS_DFSDM_CHANNEL_INPUT(hdfsdm_channel->Init.Input.Multiplexer));
assert_param(IS_DFSDM_CHANNEL_DATA_PACKING(hdfsdm_channel->Init.Input.DataPacking));
assert_param(IS_DFSDM_CHANNEL_INPUT_PINS(hdfsdm_channel->Init.Input.Pins));
assert_param(IS_DFSDM_CHANNEL_SERIAL_INTERFACE_TYPE(hdfsdm_channel->Init.SerialInterface.Type));
assert_param(IS_DFSDM_CHANNEL_SPI_CLOCK(hdfsdm_channel->Init.SerialInterface.SpiClock));
assert_param(IS_DFSDM_CHANNEL_FILTER_ORDER(hdfsdm_channel->Init.Awd.FilterOrder));
assert_param(IS_DFSDM_CHANNEL_FILTER_OVS_RATIO(hdfsdm_channel->Init.Awd.Oversampling));
assert_param(IS_DFSDM_CHANNEL_OFFSET(hdfsdm_channel->Init.Offset));
assert_param(IS_DFSDM_CHANNEL_RIGHT_BIT_SHIFT(hdfsdm_channel->Init.RightBitShift));
#if defined(DFSDM2_Channel0)
if(IS_DFSDM1_CHANNEL_INSTANCE(hdfsdm_channel->Instance))
{
channelCounterPtr = &v_dfsdm1ChannelCounter;
channelHandleTable = a_dfsdm1ChannelHandle;
channel0Instance = DFSDM1_Channel0;
}if (IS_DFSDM1_CHANNEL_INSTANCE(hdfsdm_channel->Instance)) { ... }
else
{
channelCounterPtr = &v_dfsdm2ChannelCounter;
channelHandleTable = a_dfsdm2ChannelHandle;
channel0Instance = DFSDM2_Channel0;
}else { ... }
if(channelHandleTable[DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance)] != NULL)
{
return HAL_ERROR;
}if (channelHandleTable[DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance)] != NULL) { ... }
#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
hdfsdm_channel->CkabCallback = HAL_DFSDM_ChannelCkabCallback;
hdfsdm_channel->ScdCallback = HAL_DFSDM_ChannelScdCallback;
if(hdfsdm_channel->MspInitCallback == NULL)
{
hdfsdm_channel->MspInitCallback = HAL_DFSDM_ChannelMspInit;
}if (hdfsdm_channel->MspInitCallback == NULL) { ... }
hdfsdm_channel->MspInitCallback(hdfsdm_channel);/* ... */
#else
HAL_DFSDM_ChannelMspInit(hdfsdm_channel);/* ... */
#endif
(*channelCounterPtr)++;
if(*channelCounterPtr == 1U)
{
assert_param(IS_DFSDM_CHANNEL_OUTPUT_CLOCK(hdfsdm_channel->Init.OutputClock.Selection));
channel0Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_CKOUTSRC);
channel0Instance->CHCFGR1 |= hdfsdm_channel->Init.OutputClock.Selection;
channel0Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_CKOUTDIV);
if(hdfsdm_channel->Init.OutputClock.Activation == ENABLE)
{
assert_param(IS_DFSDM_CHANNEL_OUTPUT_CLOCK_DIVIDER(hdfsdm_channel->Init.OutputClock.Divider));
channel0Instance->CHCFGR1 |= (uint32_t) ((hdfsdm_channel->Init.OutputClock.Divider - 1U) <<
DFSDM_CHCFGR1_CKOUTDIV_Pos);
}if (hdfsdm_channel->Init.OutputClock.Activation == ENABLE) { ... }
channel0Instance->CHCFGR1 |= DFSDM_CHCFGR1_DFSDMEN;
}if (*channelCounterPtr == 1U) { ... }
hdfsdm_channel->Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_DATPACK | DFSDM_CHCFGR1_DATMPX |
DFSDM_CHCFGR1_CHINSEL);
hdfsdm_channel->Instance->CHCFGR1 |= (hdfsdm_channel->Init.Input.Multiplexer |
hdfsdm_channel->Init.Input.DataPacking |
hdfsdm_channel->Init.Input.Pins);
hdfsdm_channel->Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_SITP | DFSDM_CHCFGR1_SPICKSEL);
hdfsdm_channel->Instance->CHCFGR1 |= (hdfsdm_channel->Init.SerialInterface.Type |
hdfsdm_channel->Init.SerialInterface.SpiClock);
hdfsdm_channel->Instance->CHAWSCDR &= ~(DFSDM_CHAWSCDR_AWFORD | DFSDM_CHAWSCDR_AWFOSR);
hdfsdm_channel->Instance->CHAWSCDR |= (hdfsdm_channel->Init.Awd.FilterOrder |
((hdfsdm_channel->Init.Awd.Oversampling - 1U) << DFSDM_CHAWSCDR_AWFOSR_Pos));
hdfsdm_channel->Instance->CHCFGR2 &= ~(DFSDM_CHCFGR2_OFFSET | DFSDM_CHCFGR2_DTRBS);
hdfsdm_channel->Instance->CHCFGR2 |= (((uint32_t) hdfsdm_channel->Init.Offset << DFSDM_CHCFGR2_OFFSET_Pos) |
(hdfsdm_channel->Init.RightBitShift << DFSDM_CHCFGR2_DTRBS_Pos));
hdfsdm_channel->Instance->CHCFGR1 |= DFSDM_CHCFGR1_CHEN;
hdfsdm_channel->State = HAL_DFSDM_CHANNEL_STATE_READY;
channelHandleTable[DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance)] = hdfsdm_channel;
/* ... */
#else
if(a_dfsdm1ChannelHandle[DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance)] != NULL)
{
return HAL_ERROR;
}if (a_dfsdm1ChannelHandle[DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance)] != NULL) { ... }
#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
hdfsdm_channel->CkabCallback = HAL_DFSDM_ChannelCkabCallback;
hdfsdm_channel->ScdCallback = HAL_DFSDM_ChannelScdCallback;
if(hdfsdm_channel->MspInitCallback == NULL)
{
hdfsdm_channel->MspInitCallback = HAL_DFSDM_ChannelMspInit;
}if (hdfsdm_channel->MspInitCallback == NULL) { ... }
hdfsdm_channel->MspInitCallback(hdfsdm_channel);/* ... */
#else
HAL_DFSDM_ChannelMspInit(hdfsdm_channel);/* ... */
#endif
v_dfsdm1ChannelCounter++;
if(v_dfsdm1ChannelCounter == 1U)
{
assert_param(IS_DFSDM_CHANNEL_OUTPUT_CLOCK(hdfsdm_channel->Init.OutputClock.Selection));
DFSDM1_Channel0->CHCFGR1 &= ~(DFSDM_CHCFGR1_CKOUTSRC);
DFSDM1_Channel0->CHCFGR1 |= hdfsdm_channel->Init.OutputClock.Selection;
DFSDM1_Channel0->CHCFGR1 &= ~(DFSDM_CHCFGR1_CKOUTDIV);
if(hdfsdm_channel->Init.OutputClock.Activation == ENABLE)
{
assert_param(IS_DFSDM_CHANNEL_OUTPUT_CLOCK_DIVIDER(hdfsdm_channel->Init.OutputClock.Divider));
DFSDM1_Channel0->CHCFGR1 |= (uint32_t) ((hdfsdm_channel->Init.OutputClock.Divider - 1U) <<
DFSDM_CHCFGR1_CKOUTDIV_Pos);
}if (hdfsdm_channel->Init.OutputClock.Activation == ENABLE) { ... }
DFSDM1_Channel0->CHCFGR1 |= DFSDM_CHCFGR1_DFSDMEN;
}if (v_dfsdm1ChannelCounter == 1U) { ... }
hdfsdm_channel->Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_DATPACK | DFSDM_CHCFGR1_DATMPX |
DFSDM_CHCFGR1_CHINSEL);
hdfsdm_channel->Instance->CHCFGR1 |= (hdfsdm_channel->Init.Input.Multiplexer |
hdfsdm_channel->Init.Input.DataPacking |
hdfsdm_channel->Init.Input.Pins);
hdfsdm_channel->Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_SITP | DFSDM_CHCFGR1_SPICKSEL);
hdfsdm_channel->Instance->CHCFGR1 |= (hdfsdm_channel->Init.SerialInterface.Type |
hdfsdm_channel->Init.SerialInterface.SpiClock);
hdfsdm_channel->Instance->CHAWSCDR &= ~(DFSDM_CHAWSCDR_AWFORD | DFSDM_CHAWSCDR_AWFOSR);
hdfsdm_channel->Instance->CHAWSCDR |= (hdfsdm_channel->Init.Awd.FilterOrder |
((hdfsdm_channel->Init.Awd.Oversampling - 1U) << DFSDM_CHAWSCDR_AWFOSR_Pos));
hdfsdm_channel->Instance->CHCFGR2 &= ~(DFSDM_CHCFGR2_OFFSET | DFSDM_CHCFGR2_DTRBS);
hdfsdm_channel->Instance->CHCFGR2 |= (((uint32_t) hdfsdm_channel->Init.Offset << DFSDM_CHCFGR2_OFFSET_Pos) |
(hdfsdm_channel->Init.RightBitShift << DFSDM_CHCFGR2_DTRBS_Pos));
hdfsdm_channel->Instance->CHCFGR1 |= DFSDM_CHCFGR1_CHEN;
hdfsdm_channel->State = HAL_DFSDM_CHANNEL_STATE_READY;
a_dfsdm1ChannelHandle[DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance)] = hdfsdm_channel;/* ... */
#endif
return HAL_OK;
}HAL_DFSDM_ChannelInit (DFSDM_Channel_HandleTypeDef *hdfsdm_channel) { ... }
/* ... */
HAL_StatusTypeDef HAL_DFSDM_ChannelDeInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
{
#if defined(DFSDM2_Channel0)
__IO uint32_t* channelCounterPtr;
DFSDM_Channel_HandleTypeDef **channelHandleTable;
DFSDM_Channel_TypeDef* channel0Instance;/* ... */
#endif
if(hdfsdm_channel == NULL)
{
return HAL_ERROR;
}if (hdfsdm_channel == NULL) { ... }
assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance));
#if defined(DFSDM2_Channel0)
if(IS_DFSDM1_CHANNEL_INSTANCE(hdfsdm_channel->Instance))
{
channelCounterPtr = &v_dfsdm1ChannelCounter;
channelHandleTable = a_dfsdm1ChannelHandle;
channel0Instance = DFSDM1_Channel0;
}if (IS_DFSDM1_CHANNEL_INSTANCE(hdfsdm_channel->Instance)) { ... }
else
{
channelCounterPtr = &v_dfsdm2ChannelCounter;
channelHandleTable = a_dfsdm2ChannelHandle;
channel0Instance = DFSDM2_Channel0;
}else { ... }
if(channelHandleTable[DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance)] == NULL)
{
return HAL_ERROR;
}if (channelHandleTable[DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance)] == NULL) { ... }
hdfsdm_channel->Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_CHEN);
(*channelCounterPtr)--;
if(*channelCounterPtr == 0U)
{
channel0Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_DFSDMEN);
}if (*channelCounterPtr == 0U) { ... }
#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
if(hdfsdm_channel->MspDeInitCallback == NULL)
{
hdfsdm_channel->MspDeInitCallback = HAL_DFSDM_ChannelMspDeInit;
}if (hdfsdm_channel->MspDeInitCallback == NULL) { ... }
hdfsdm_channel->MspDeInitCallback(hdfsdm_channel);/* ... */
#else
HAL_DFSDM_ChannelMspDeInit(hdfsdm_channel);
#endif
hdfsdm_channel->State = HAL_DFSDM_CHANNEL_STATE_RESET;
channelHandleTable[DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance)] = NULL;/* ... */
#else
if(a_dfsdm1ChannelHandle[DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance)] == NULL)
{
return HAL_ERROR;
}if (a_dfsdm1ChannelHandle[DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance)] == NULL) { ... }
hdfsdm_channel->Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_CHEN);
v_dfsdm1ChannelCounter--;
if(v_dfsdm1ChannelCounter == 0U)
{
DFSDM1_Channel0->CHCFGR1 &= ~(DFSDM_CHCFGR1_DFSDMEN);
}if (v_dfsdm1ChannelCounter == 0U) { ... }
#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
if(hdfsdm_channel->MspDeInitCallback == NULL)
{
hdfsdm_channel->MspDeInitCallback = HAL_DFSDM_ChannelMspDeInit;
}if (hdfsdm_channel->MspDeInitCallback == NULL) { ... }
hdfsdm_channel->MspDeInitCallback(hdfsdm_channel);/* ... */
#else
HAL_DFSDM_ChannelMspDeInit(hdfsdm_channel);
#endif
hdfsdm_channel->State = HAL_DFSDM_CHANNEL_STATE_RESET;
a_dfsdm1ChannelHandle[DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance)] = (DFSDM_Channel_HandleTypeDef *) NULL;/* ... */
#endif
return HAL_OK;
}HAL_DFSDM_ChannelDeInit (DFSDM_Channel_HandleTypeDef *hdfsdm_channel) { ... }
/* ... */
__weak void HAL_DFSDM_ChannelMspInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
{
UNUSED(hdfsdm_channel);
/* ... */
}HAL_DFSDM_ChannelMspInit (DFSDM_Channel_HandleTypeDef *hdfsdm_channel) { ... }
/* ... */
__weak void HAL_DFSDM_ChannelMspDeInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
{
UNUSED(hdfsdm_channel);
/* ... */
}HAL_DFSDM_ChannelMspDeInit (DFSDM_Channel_HandleTypeDef *hdfsdm_channel) { ... }
#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
/* ... */
HAL_StatusTypeDef HAL_DFSDM_Channel_RegisterCallback(DFSDM_Channel_HandleTypeDef *hdfsdm_channel,
HAL_DFSDM_Channel_CallbackIDTypeDef CallbackID,
pDFSDM_Channel_CallbackTypeDef pCallback)
{
HAL_StatusTypeDef status = HAL_OK;
if(pCallback == NULL)
{
status = HAL_ERROR;
}if (pCallback == NULL) { ... }
else
{
if(HAL_DFSDM_CHANNEL_STATE_READY == hdfsdm_channel->State)
{
switch (CallbackID)
{
case HAL_DFSDM_CHANNEL_CKAB_CB_ID :
hdfsdm_channel->CkabCallback = pCallback;
break;case HAL_DFSDM_CHANNEL_CKAB_CB_ID :
case HAL_DFSDM_CHANNEL_SCD_CB_ID :
hdfsdm_channel->ScdCallback = pCallback;
break;case HAL_DFSDM_CHANNEL_SCD_CB_ID :
case HAL_DFSDM_CHANNEL_MSPINIT_CB_ID :
hdfsdm_channel->MspInitCallback = pCallback;
break;case HAL_DFSDM_CHANNEL_MSPINIT_CB_ID :
case HAL_DFSDM_CHANNEL_MSPDEINIT_CB_ID :
hdfsdm_channel->MspDeInitCallback = pCallback;
break;case HAL_DFSDM_CHANNEL_MSPDEINIT_CB_ID :
default :
status = HAL_ERROR;
break;default
}switch (CallbackID) { ... }
}if (HAL_DFSDM_CHANNEL_STATE_READY == hdfsdm_channel->State) { ... }
else if(HAL_DFSDM_CHANNEL_STATE_RESET == hdfsdm_channel->State)
{
switch (CallbackID)
{
case HAL_DFSDM_CHANNEL_MSPINIT_CB_ID :
hdfsdm_channel->MspInitCallback = pCallback;
break;case HAL_DFSDM_CHANNEL_MSPINIT_CB_ID :
case HAL_DFSDM_CHANNEL_MSPDEINIT_CB_ID :
hdfsdm_channel->MspDeInitCallback = pCallback;
break;case HAL_DFSDM_CHANNEL_MSPDEINIT_CB_ID :
default :
status = HAL_ERROR;
break;default
}switch (CallbackID) { ... }
}else if (HAL_DFSDM_CHANNEL_STATE_RESET == hdfsdm_channel->State) { ... }
else
{
status = HAL_ERROR;
}else { ... }
}else { ... }
return status;
}HAL_DFSDM_Channel_RegisterCallback (DFSDM_Channel_HandleTypeDef *hdfsdm_channel, HAL_DFSDM_Channel_CallbackIDTypeDef CallbackID, pDFSDM_Channel_CallbackTypeDef pCallback) { ... }
/* ... */
HAL_StatusTypeDef HAL_DFSDM_Channel_UnRegisterCallback(DFSDM_Channel_HandleTypeDef *hdfsdm_channel,
HAL_DFSDM_Channel_CallbackIDTypeDef CallbackID)
{
HAL_StatusTypeDef status = HAL_OK;
if(HAL_DFSDM_CHANNEL_STATE_READY == hdfsdm_channel->State)
{
switch (CallbackID)
{
case HAL_DFSDM_CHANNEL_CKAB_CB_ID :
hdfsdm_channel->CkabCallback = HAL_DFSDM_ChannelCkabCallback;
break;case HAL_DFSDM_CHANNEL_CKAB_CB_ID :
case HAL_DFSDM_CHANNEL_SCD_CB_ID :
hdfsdm_channel->ScdCallback = HAL_DFSDM_ChannelScdCallback;
break;case HAL_DFSDM_CHANNEL_SCD_CB_ID :
case HAL_DFSDM_CHANNEL_MSPINIT_CB_ID :
hdfsdm_channel->MspInitCallback = HAL_DFSDM_ChannelMspInit;
break;case HAL_DFSDM_CHANNEL_MSPINIT_CB_ID :
case HAL_DFSDM_CHANNEL_MSPDEINIT_CB_ID :
hdfsdm_channel->MspDeInitCallback = HAL_DFSDM_ChannelMspDeInit;
break;case HAL_DFSDM_CHANNEL_MSPDEINIT_CB_ID :
default :
status = HAL_ERROR;
break;default
}switch (CallbackID) { ... }
}if (HAL_DFSDM_CHANNEL_STATE_READY == hdfsdm_channel->State) { ... }
else if(HAL_DFSDM_CHANNEL_STATE_RESET == hdfsdm_channel->State)
{
switch (CallbackID)
{
case HAL_DFSDM_CHANNEL_MSPINIT_CB_ID :
hdfsdm_channel->MspInitCallback = HAL_DFSDM_ChannelMspInit;
break;case HAL_DFSDM_CHANNEL_MSPINIT_CB_ID :
case HAL_DFSDM_CHANNEL_MSPDEINIT_CB_ID :
hdfsdm_channel->MspDeInitCallback = HAL_DFSDM_ChannelMspDeInit;
break;case HAL_DFSDM_CHANNEL_MSPDEINIT_CB_ID :
default :
status = HAL_ERROR;
break;default
}switch (CallbackID) { ... }
}else if (HAL_DFSDM_CHANNEL_STATE_RESET == hdfsdm_channel->State) { ... }
else
{
status = HAL_ERROR;
}else { ... }
return status;
}HAL_DFSDM_Channel_UnRegisterCallback (DFSDM_Channel_HandleTypeDef *hdfsdm_channel, HAL_DFSDM_Channel_CallbackIDTypeDef CallbackID) { ... }
/* ... */#endif
/* ... */
/* ... */
/* ... */
HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStart(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
{
HAL_StatusTypeDef status = HAL_OK;
uint32_t tickstart;
uint32_t channel;
#if defined(DFSDM2_Channel0)
DFSDM_Filter_TypeDef* filter0Instance;
#endif
assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance));
if(hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY)
{
status = HAL_ERROR;
}if (hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY) { ... }
else
{
#if defined (DFSDM2_Channel0)
if(IS_DFSDM1_CHANNEL_INSTANCE(hdfsdm_channel->Instance))
{
filter0Instance = DFSDM1_Filter0;
}if (IS_DFSDM1_CHANNEL_INSTANCE(hdfsdm_channel->Instance)) { ... }
else
{
filter0Instance = DFSDM2_Filter0;
}else { ... }
channel = DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance);
tickstart = HAL_GetTick();
while((((filter0Instance->FLTISR & DFSDM_FLTISR_CKABF) >> (DFSDM_FLTISR_CKABF_Pos + channel)) & 1U) != 0U)
{
filter0Instance->FLTICR = (1U << (DFSDM_FLTICR_CLRCKABF_Pos + channel));
if((HAL_GetTick()-tickstart) > DFSDM_CKAB_TIMEOUT)
{
status = HAL_TIMEOUT;
break;
}if ((HAL_GetTick()-tickstart) > DFSDM_CKAB_TIMEOUT) { ... }
}while ((((filter0Instance->FLTISR & DFSDM_FLTISR_CKABF) >> (DFSDM_FLTISR_CKABF_Pos + channel)) & 1U) != 0U) { ... }
/* ... */#else
channel = DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance);
tickstart = HAL_GetTick();
while((((DFSDM1_Filter0->FLTISR & DFSDM_FLTISR_CKABF) >> (DFSDM_FLTISR_CKABF_Pos + channel)) & 1U) != 0U)
{
DFSDM1_Filter0->FLTICR = (1U << (DFSDM_FLTICR_CLRCKABF_Pos + channel));
if((HAL_GetTick()-tickstart) > DFSDM_CKAB_TIMEOUT)
{
status = HAL_TIMEOUT;
break;
}if ((HAL_GetTick()-tickstart) > DFSDM_CKAB_TIMEOUT) { ... }
}while ((((DFSDM1_Filter0->FLTISR & DFSDM_FLTISR_CKABF) >> (DFSDM_FLTISR_CKABF_Pos + channel)) & 1U) != 0U) { ... }
/* ... */#endif
if(status == HAL_OK)
{
hdfsdm_channel->Instance->CHCFGR1 |= DFSDM_CHCFGR1_CKABEN;
}if (status == HAL_OK) { ... }
}else { ... }
return status;
}HAL_DFSDM_ChannelCkabStart (DFSDM_Channel_HandleTypeDef *hdfsdm_channel) { ... }
/* ... */
HAL_StatusTypeDef HAL_DFSDM_ChannelPollForCkab(const DFSDM_Channel_HandleTypeDef *hdfsdm_channel,
uint32_t Timeout)
{
uint32_t tickstart;
uint32_t channel;
#if defined(DFSDM2_Channel0)
DFSDM_Filter_TypeDef* filter0Instance;
#endif
assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance));
if(hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY)
{
return HAL_ERROR;
}if (hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY) { ... }
else
{
#if defined(DFSDM2_Channel0)
if(IS_DFSDM1_CHANNEL_INSTANCE(hdfsdm_channel->Instance))
{
filter0Instance = DFSDM1_Filter0;
}if (IS_DFSDM1_CHANNEL_INSTANCE(hdfsdm_channel->Instance)) { ... }
else
{
filter0Instance = DFSDM2_Filter0;
}else { ... }
channel = DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance);
tickstart = HAL_GetTick();
while((((filter0Instance->FLTISR & DFSDM_FLTISR_CKABF) >> (DFSDM_FLTISR_CKABF_Pos + channel)) & 1U) == 0U)
{
if(Timeout != HAL_MAX_DELAY)
{
if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout))
{
return HAL_TIMEOUT;
}if ((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout)) { ... }
}if (Timeout != HAL_MAX_DELAY) { ... }
}while ((((filter0Instance->FLTISR & DFSDM_FLTISR_CKABF) >> (DFSDM_FLTISR_CKABF_Pos + channel)) & 1U) == 0U) { ... }
filter0Instance->FLTICR = (1U << (DFSDM_FLTICR_CLRCKABF_Pos + channel));/* ... */
#else
channel = DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance);
tickstart = HAL_GetTick();
while((((DFSDM1_Filter0->FLTISR & DFSDM_FLTISR_CKABF) >> (DFSDM_FLTISR_CKABF_Pos + channel)) & 1U) == 0U)
{
if(Timeout != HAL_MAX_DELAY)
{
if(((HAL_GetTick()-tickstart) > Timeout) || (Timeout == 0U))
{
return HAL_TIMEOUT;
}if (((HAL_GetTick()-tickstart) > Timeout) || (Timeout == 0U)) { ... }
}if (Timeout != HAL_MAX_DELAY) { ... }
}while ((((DFSDM1_Filter0->FLTISR & DFSDM_FLTISR_CKABF) >> (DFSDM_FLTISR_CKABF_Pos + channel)) & 1U) == 0U) { ... }
DFSDM1_Filter0->FLTICR = (1U << (DFSDM_FLTICR_CLRCKABF_Pos + channel));/* ... */
#endif
return HAL_OK;
}else { ... }
}HAL_DFSDM_ChannelPollForCkab (const DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Timeout) { ... }
/* ... */
HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStop(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
{
HAL_StatusTypeDef status = HAL_OK;
uint32_t channel;
#if defined(DFSDM2_Channel0)
DFSDM_Filter_TypeDef* filter0Instance;
#endif
assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance));
if(hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY)
{
status = HAL_ERROR;
}if (hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY) { ... }
else
{
#if defined(DFSDM2_Channel0)
if(IS_DFSDM1_CHANNEL_INSTANCE(hdfsdm_channel->Instance))
{
filter0Instance = DFSDM1_Filter0;
}if (IS_DFSDM1_CHANNEL_INSTANCE(hdfsdm_channel->Instance)) { ... }
else
{
filter0Instance = DFSDM2_Filter0;
}else { ... }
hdfsdm_channel->Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_CKABEN);
channel = DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance);
filter0Instance->FLTICR = (1U << (DFSDM_FLTICR_CLRCKABF_Pos + channel));
/* ... */
#else
hdfsdm_channel->Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_CKABEN);
channel = DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance);
DFSDM1_Filter0->FLTICR = (1U << (DFSDM_FLTICR_CLRCKABF_Pos + channel));/* ... */
#endif
}else { ... }
return status;
}HAL_DFSDM_ChannelCkabStop (DFSDM_Channel_HandleTypeDef *hdfsdm_channel) { ... }
/* ... */
HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStart_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
{
HAL_StatusTypeDef status = HAL_OK;
uint32_t channel;
uint32_t tickstart;
#if defined(DFSDM2_Channel0)
DFSDM_Filter_TypeDef* filter0Instance;
#endif
assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance));
if(hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY)
{
status = HAL_ERROR;
}if (hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY) { ... }
else
{
#if defined(DFSDM2_Channel0)
if(IS_DFSDM1_CHANNEL_INSTANCE(hdfsdm_channel->Instance))
{
filter0Instance = DFSDM1_Filter0;
}if (IS_DFSDM1_CHANNEL_INSTANCE(hdfsdm_channel->Instance)) { ... }
else
{
filter0Instance = DFSDM2_Filter0;
}else { ... }
channel = DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance);
tickstart = HAL_GetTick();
while((((filter0Instance->FLTISR & DFSDM_FLTISR_CKABF) >> (DFSDM_FLTISR_CKABF_Pos + channel)) & 1U) != 0U)
{
filter0Instance->FLTICR = (1U << (DFSDM_FLTICR_CLRCKABF_Pos + channel));
if((HAL_GetTick()-tickstart) > DFSDM_CKAB_TIMEOUT)
{
status = HAL_TIMEOUT;
break;
}if ((HAL_GetTick()-tickstart) > DFSDM_CKAB_TIMEOUT) { ... }
}while ((((filter0Instance->FLTISR & DFSDM_FLTISR_CKABF) >> (DFSDM_FLTISR_CKABF_Pos + channel)) & 1U) != 0U) { ... }
if(status == HAL_OK)
{
filter0Instance->FLTCR2 |= DFSDM_FLTCR2_CKABIE;
hdfsdm_channel->Instance->CHCFGR1 |= DFSDM_CHCFGR1_CKABEN;
}if (status == HAL_OK) { ... }
/* ... */#else
channel = DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance);
tickstart = HAL_GetTick();
while((((DFSDM1_Filter0->FLTISR & DFSDM_FLTISR_CKABF) >> (DFSDM_FLTISR_CKABF_Pos + channel)) & 1U) != 0U)
{
DFSDM1_Filter0->FLTICR = (1U << (DFSDM_FLTICR_CLRCKABF_Pos + channel));
if((HAL_GetTick()-tickstart) > DFSDM_CKAB_TIMEOUT)
{
status = HAL_TIMEOUT;
break;
}if ((HAL_GetTick()-tickstart) > DFSDM_CKAB_TIMEOUT) { ... }
}while ((((DFSDM1_Filter0->FLTISR & DFSDM_FLTISR_CKABF) >> (DFSDM_FLTISR_CKABF_Pos + channel)) & 1U) != 0U) { ... }
if(status == HAL_OK)
{
DFSDM1_Filter0->FLTCR2 |= DFSDM_FLTCR2_CKABIE;
hdfsdm_channel->Instance->CHCFGR1 |= DFSDM_CHCFGR1_CKABEN;
}if (status == HAL_OK) { ... }
/* ... */
#endif
}else { ... }
return status;
}HAL_DFSDM_ChannelCkabStart_IT (DFSDM_Channel_HandleTypeDef *hdfsdm_channel) { ... }
/* ... */
__weak void HAL_DFSDM_ChannelCkabCallback(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
{
UNUSED(hdfsdm_channel);
/* ... */
}HAL_DFSDM_ChannelCkabCallback (DFSDM_Channel_HandleTypeDef *hdfsdm_channel) { ... }
/* ... */
HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStop_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
{
HAL_StatusTypeDef status = HAL_OK;
uint32_t channel;
#if defined(DFSDM2_Channel0)
DFSDM_Filter_TypeDef* filter0Instance;
#endif
assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance));
if(hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY)
{
status = HAL_ERROR;
}if (hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY) { ... }
else
{
#if defined(DFSDM2_Channel0)
if(IS_DFSDM1_CHANNEL_INSTANCE(hdfsdm_channel->Instance))
{
filter0Instance = DFSDM1_Filter0;
}if (IS_DFSDM1_CHANNEL_INSTANCE(hdfsdm_channel->Instance)) { ... }
else
{
filter0Instance = DFSDM2_Filter0;
}else { ... }
hdfsdm_channel->Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_CKABEN);
channel = DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance);
filter0Instance->FLTICR = (1U << (DFSDM_FLTICR_CLRCKABF_Pos + channel));
filter0Instance->FLTCR2 &= ~(DFSDM_FLTCR2_CKABIE);/* ... */
#else
hdfsdm_channel->Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_CKABEN);
channel = DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance);
DFSDM1_Filter0->FLTICR = (1U << (DFSDM_FLTICR_CLRCKABF_Pos + channel));
DFSDM1_Filter0->FLTCR2 &= ~(DFSDM_FLTCR2_CKABIE);/* ... */
#endif
}else { ... }
return status;
}HAL_DFSDM_ChannelCkabStop_IT (DFSDM_Channel_HandleTypeDef *hdfsdm_channel) { ... }
/* ... */
HAL_StatusTypeDef HAL_DFSDM_ChannelScdStart(DFSDM_Channel_HandleTypeDef *hdfsdm_channel,
uint32_t Threshold,
uint32_t BreakSignal)
{
HAL_StatusTypeDef status = HAL_OK;
assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance));
assert_param(IS_DFSDM_CHANNEL_SCD_THRESHOLD(Threshold));
assert_param(IS_DFSDM_BREAK_SIGNALS(BreakSignal));
if(hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY)
{
status = HAL_ERROR;
}if (hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY) { ... }
else
{
hdfsdm_channel->Instance->CHAWSCDR &= ~(DFSDM_CHAWSCDR_BKSCD | DFSDM_CHAWSCDR_SCDT);
hdfsdm_channel->Instance->CHAWSCDR |= ((BreakSignal << DFSDM_CHAWSCDR_BKSCD_Pos) | \
Threshold);
hdfsdm_channel->Instance->CHCFGR1 |= DFSDM_CHCFGR1_SCDEN;
}else { ... }
return status;
}HAL_DFSDM_ChannelScdStart (DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Threshold, uint32_t BreakSignal) { ... }
/* ... */
HAL_StatusTypeDef HAL_DFSDM_ChannelPollForScd(const DFSDM_Channel_HandleTypeDef *hdfsdm_channel,
uint32_t Timeout)
{
uint32_t tickstart;
uint32_t channel;
#if defined(DFSDM2_Channel0)
DFSDM_Filter_TypeDef* filter0Instance;
#endif
assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance));
if(hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY)
{
return HAL_ERROR;
}if (hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY) { ... }
else
{
channel = DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance);
#if defined(DFSDM2_Channel0)
if(IS_DFSDM1_CHANNEL_INSTANCE(hdfsdm_channel->Instance))
{
filter0Instance = DFSDM1_Filter0;
}if (IS_DFSDM1_CHANNEL_INSTANCE(hdfsdm_channel->Instance)) { ... }
else
{
filter0Instance = DFSDM2_Filter0;
}else { ... }
tickstart = HAL_GetTick();
while(((filter0Instance->FLTISR & DFSDM_FLTISR_SCDF) >> (DFSDM_FLTISR_SCDF_Pos + channel)) == 0U)
{
if(Timeout != HAL_MAX_DELAY)
{
if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout))
{
return HAL_TIMEOUT;
}if ((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout)) { ... }
}if (Timeout != HAL_MAX_DELAY) { ... }
}while (((filter0Instance->FLTISR & DFSDM_FLTISR_SCDF) >> (DFSDM_FLTISR_SCDF_Pos + channel)) == 0U) { ... }
filter0Instance->FLTICR = (1U << (DFSDM_FLTICR_CLRSCDF_Pos + channel));
/* ... */
#else
tickstart = HAL_GetTick();
while(((DFSDM1_Filter0->FLTISR & DFSDM_FLTISR_SCDF) >> (DFSDM_FLTISR_SCDF_Pos + channel)) == 0U)
{
if(Timeout != HAL_MAX_DELAY)
{
if(((HAL_GetTick()-tickstart) > Timeout) || (Timeout == 0U))
{
return HAL_TIMEOUT;
}if (((HAL_GetTick()-tickstart) > Timeout) || (Timeout == 0U)) { ... }
}if (Timeout != HAL_MAX_DELAY) { ... }
}while (((DFSDM1_Filter0->FLTISR & DFSDM_FLTISR_SCDF) >> (DFSDM_FLTISR_SCDF_Pos + channel)) == 0U) { ... }
DFSDM1_Filter0->FLTICR = (1U << (DFSDM_FLTICR_CLRSCDF_Pos + channel));/* ... */
#endif
return HAL_OK;
}else { ... }
}HAL_DFSDM_ChannelPollForScd (const DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Timeout) { ... }
/* ... */
HAL_StatusTypeDef HAL_DFSDM_ChannelScdStop(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
{
HAL_StatusTypeDef status = HAL_OK;
uint32_t channel;
#if defined(DFSDM2_Channel0)
DFSDM_Filter_TypeDef* filter0Instance;
#endif
assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance));
if(hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY)
{
status = HAL_ERROR;
}if (hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY) { ... }
else
{
hdfsdm_channel->Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_SCDEN);
channel = DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance);
#if defined(DFSDM2_Channel0)
if(IS_DFSDM1_CHANNEL_INSTANCE(hdfsdm_channel->Instance))
{
filter0Instance = DFSDM1_Filter0;
}if (IS_DFSDM1_CHANNEL_INSTANCE(hdfsdm_channel->Instance)) { ... }
else
{
filter0Instance = DFSDM2_Filter0;
}else { ... }
filter0Instance->FLTICR = (1U << (DFSDM_FLTICR_CLRSCDF_Pos + channel));/* ... */
#else
DFSDM1_Filter0->FLTICR = (1U << (DFSDM_FLTICR_CLRSCDF_Pos + channel));
#endif
}else { ... }
return status;
}HAL_DFSDM_ChannelScdStop (DFSDM_Channel_HandleTypeDef *hdfsdm_channel) { ... }
/* ... */
HAL_StatusTypeDef HAL_DFSDM_ChannelScdStart_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel,
uint32_t Threshold,
uint32_t BreakSignal)
{
HAL_StatusTypeDef status = HAL_OK;
#if defined(DFSDM2_Channel0)
DFSDM_Filter_TypeDef* filter0Instance;
#endif
assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance));
assert_param(IS_DFSDM_CHANNEL_SCD_THRESHOLD(Threshold));
assert_param(IS_DFSDM_BREAK_SIGNALS(BreakSignal));
if(hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY)
{
status = HAL_ERROR;
}if (hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY) { ... }
else
{
#if defined(DFSDM2_Channel0)
if(IS_DFSDM1_CHANNEL_INSTANCE(hdfsdm_channel->Instance))
{
filter0Instance = DFSDM1_Filter0;
}if (IS_DFSDM1_CHANNEL_INSTANCE(hdfsdm_channel->Instance)) { ... }
else
{
filter0Instance = DFSDM2_Filter0;
}else { ... }
filter0Instance->FLTCR2 |= DFSDM_FLTCR2_SCDIE;/* ... */
#else
DFSDM1_Filter0->FLTCR2 |= DFSDM_FLTCR2_SCDIE;/* ... */
#endif
hdfsdm_channel->Instance->CHAWSCDR &= ~(DFSDM_CHAWSCDR_BKSCD | DFSDM_CHAWSCDR_SCDT);
hdfsdm_channel->Instance->CHAWSCDR |= ((BreakSignal << DFSDM_CHAWSCDR_BKSCD_Pos) | \
Threshold);
hdfsdm_channel->Instance->CHCFGR1 |= DFSDM_CHCFGR1_SCDEN;
}else { ... }
return status;
}HAL_DFSDM_ChannelScdStart_IT (DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Threshold, uint32_t BreakSignal) { ... }
/* ... */
__weak void HAL_DFSDM_ChannelScdCallback(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
{
UNUSED(hdfsdm_channel);
/* ... */
}HAL_DFSDM_ChannelScdCallback (DFSDM_Channel_HandleTypeDef *hdfsdm_channel) { ... }
/* ... */
HAL_StatusTypeDef HAL_DFSDM_ChannelScdStop_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
{
HAL_StatusTypeDef status = HAL_OK;
uint32_t channel;
#if defined(DFSDM2_Channel0)
DFSDM_Filter_TypeDef* filter0Instance;
#endif
assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance));
if(hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY)
{
status = HAL_ERROR;
}if (hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY) { ... }
else
{
hdfsdm_channel->Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_SCDEN);
channel = DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance);
#if defined(DFSDM2_Channel0)
if(IS_DFSDM1_CHANNEL_INSTANCE(hdfsdm_channel->Instance))
{
filter0Instance = DFSDM1_Filter0;
}if (IS_DFSDM1_CHANNEL_INSTANCE(hdfsdm_channel->Instance)) { ... }
else
{
filter0Instance = DFSDM2_Filter0;
}else { ... }
filter0Instance->FLTICR = (1U << (DFSDM_FLTICR_CLRSCDF_Pos + channel));
filter0Instance->FLTCR2 &= ~(DFSDM_FLTCR2_SCDIE);/* ... */
#else
DFSDM1_Filter0->FLTICR = (1U << (DFSDM_FLTICR_CLRSCDF_Pos + channel));
DFSDM1_Filter0->FLTCR2 &= ~(DFSDM_FLTCR2_SCDIE);/* ... */
#endif
}else { ... }
return status;
}HAL_DFSDM_ChannelScdStop_IT (DFSDM_Channel_HandleTypeDef *hdfsdm_channel) { ... }
/* ... */
int16_t HAL_DFSDM_ChannelGetAwdValue(const DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
{
return (int16_t) hdfsdm_channel->Instance->CHWDATAR;
}HAL_DFSDM_ChannelGetAwdValue (const DFSDM_Channel_HandleTypeDef *hdfsdm_channel) { ... }
/* ... */
HAL_StatusTypeDef HAL_DFSDM_ChannelModifyOffset(DFSDM_Channel_HandleTypeDef *hdfsdm_channel,
int32_t Offset)
{
HAL_StatusTypeDef status = HAL_OK;
assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance));
assert_param(IS_DFSDM_CHANNEL_OFFSET(Offset));
if(hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY)
{
status = HAL_ERROR;
}if (hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY) { ... }
else
{
hdfsdm_channel->Instance->CHCFGR2 &= ~(DFSDM_CHCFGR2_OFFSET);
hdfsdm_channel->Instance->CHCFGR2 |= ((uint32_t) Offset << DFSDM_CHCFGR2_OFFSET_Pos);
}else { ... }
return status;
}HAL_DFSDM_ChannelModifyOffset (DFSDM_Channel_HandleTypeDef *hdfsdm_channel, int32_t Offset) { ... }
/* ... */
/* ... */
/* ... */
HAL_DFSDM_Channel_StateTypeDef HAL_DFSDM_ChannelGetState(const DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
{
return hdfsdm_channel->State;
}HAL_DFSDM_ChannelGetState (const DFSDM_Channel_HandleTypeDef *hdfsdm_channel) { ... }
/* ... */
/* ... */
/* ... */
HAL_StatusTypeDef HAL_DFSDM_FilterInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
{
if(hdfsdm_filter == NULL)
{
return HAL_ERROR;
}if (hdfsdm_filter == NULL) { ... }
assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
assert_param(IS_DFSDM_FILTER_REG_TRIGGER(hdfsdm_filter->Init.RegularParam.Trigger));
assert_param(IS_FUNCTIONAL_STATE(hdfsdm_filter->Init.RegularParam.FastMode));
assert_param(IS_FUNCTIONAL_STATE(hdfsdm_filter->Init.RegularParam.DmaMode));
assert_param(IS_DFSDM_FILTER_INJ_TRIGGER(hdfsdm_filter->Init.InjectedParam.Trigger));
assert_param(IS_FUNCTIONAL_STATE(hdfsdm_filter->Init.InjectedParam.ScanMode));
assert_param(IS_FUNCTIONAL_STATE(hdfsdm_filter->Init.InjectedParam.DmaMode));
assert_param(IS_DFSDM_FILTER_SINC_ORDER(hdfsdm_filter->Init.FilterParam.SincOrder));
assert_param(IS_DFSDM_FILTER_OVS_RATIO(hdfsdm_filter->Init.FilterParam.Oversampling));
assert_param(IS_DFSDM_FILTER_INTEGRATOR_OVS_RATIO(hdfsdm_filter->Init.FilterParam.IntOversampling));
if((hdfsdm_filter->Instance == DFSDM1_Filter0) &&
((hdfsdm_filter->Init.RegularParam.Trigger == DFSDM_FILTER_SYNC_TRIGGER) ||
(hdfsdm_filter->Init.InjectedParam.Trigger == DFSDM_FILTER_SYNC_TRIGGER)))
{
return HAL_ERROR;
}if ((hdfsdm_filter->Instance == DFSDM1_Filter0) && ((hdfsdm_filter->Init.RegularParam.Trigger == DFSDM_FILTER_SYNC_TRIGGER) || (hdfsdm_filter->Init.InjectedParam.Trigger == DFSDM_FILTER_SYNC_TRIGGER))) { ... }
#if defined (DFSDM2_Channel0)
if((hdfsdm_filter->Instance == DFSDM2_Filter0) &&
((hdfsdm_filter->Init.RegularParam.Trigger == DFSDM_FILTER_SYNC_TRIGGER) ||
(hdfsdm_filter->Init.InjectedParam.Trigger == DFSDM_FILTER_SYNC_TRIGGER)))
{
return HAL_ERROR;
}if ((hdfsdm_filter->Instance == DFSDM2_Filter0) && ((hdfsdm_filter->Init.RegularParam.Trigger == DFSDM_FILTER_SYNC_TRIGGER) || (hdfsdm_filter->Init.InjectedParam.Trigger == DFSDM_FILTER_SYNC_TRIGGER))) { ... }
/* ... */#endif
hdfsdm_filter->RegularContMode = DFSDM_CONTINUOUS_CONV_OFF;
hdfsdm_filter->InjectedChannelsNbr = 1U;
hdfsdm_filter->InjConvRemaining = 1U;
hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_NONE;
#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
hdfsdm_filter->AwdCallback = HAL_DFSDM_FilterAwdCallback;
hdfsdm_filter->RegConvCpltCallback = HAL_DFSDM_FilterRegConvCpltCallback;
hdfsdm_filter->RegConvHalfCpltCallback = HAL_DFSDM_FilterRegConvHalfCpltCallback;
hdfsdm_filter->InjConvCpltCallback = HAL_DFSDM_FilterInjConvCpltCallback;
hdfsdm_filter->InjConvHalfCpltCallback = HAL_DFSDM_FilterInjConvHalfCpltCallback;
hdfsdm_filter->ErrorCallback = HAL_DFSDM_FilterErrorCallback;
if(hdfsdm_filter->MspInitCallback == NULL)
{
hdfsdm_filter->MspInitCallback = HAL_DFSDM_FilterMspInit;
}if (hdfsdm_filter->MspInitCallback == NULL) { ... }
hdfsdm_filter->MspInitCallback(hdfsdm_filter);/* ... */
#else
HAL_DFSDM_FilterMspInit(hdfsdm_filter);/* ... */
#endif
hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_RSYNC);
if(hdfsdm_filter->Init.RegularParam.FastMode == ENABLE)
{
hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_FAST;
}if (hdfsdm_filter->Init.RegularParam.FastMode == ENABLE) { ... }
else
{
hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_FAST);
}else { ... }
if(hdfsdm_filter->Init.RegularParam.DmaMode == ENABLE)
{
hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_RDMAEN;
}if (hdfsdm_filter->Init.RegularParam.DmaMode == ENABLE) { ... }
else
{
hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_RDMAEN);
}else { ... }
hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_JSYNC | DFSDM_FLTCR1_JEXTEN | DFSDM_FLTCR1_JEXTSEL);
if(hdfsdm_filter->Init.InjectedParam.Trigger == DFSDM_FILTER_EXT_TRIGGER)
{
assert_param(IS_DFSDM_FILTER_EXT_TRIG(hdfsdm_filter->Init.InjectedParam.ExtTrigger));
assert_param(IS_DFSDM_FILTER_EXT_TRIG_EDGE(hdfsdm_filter->Init.InjectedParam.ExtTriggerEdge));
hdfsdm_filter->Instance->FLTCR1 |= (hdfsdm_filter->Init.InjectedParam.ExtTrigger);
}if (hdfsdm_filter->Init.InjectedParam.Trigger == DFSDM_FILTER_EXT_TRIGGER) { ... }
if(hdfsdm_filter->Init.InjectedParam.ScanMode == ENABLE)
{
hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_JSCAN;
}if (hdfsdm_filter->Init.InjectedParam.ScanMode == ENABLE) { ... }
else
{
hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_JSCAN);
}else { ... }
if(hdfsdm_filter->Init.InjectedParam.DmaMode == ENABLE)
{
hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_JDMAEN;
}if (hdfsdm_filter->Init.InjectedParam.DmaMode == ENABLE) { ... }
else
{
hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_JDMAEN);
}else { ... }
hdfsdm_filter->Instance->FLTFCR &= ~(DFSDM_FLTFCR_FORD | DFSDM_FLTFCR_FOSR | DFSDM_FLTFCR_IOSR);
hdfsdm_filter->Instance->FLTFCR |= (hdfsdm_filter->Init.FilterParam.SincOrder |
((hdfsdm_filter->Init.FilterParam.Oversampling - 1U) << DFSDM_FLTFCR_FOSR_Pos) |
(hdfsdm_filter->Init.FilterParam.IntOversampling - 1U));
hdfsdm_filter->RegularTrigger = hdfsdm_filter->Init.RegularParam.Trigger;
hdfsdm_filter->InjectedTrigger = hdfsdm_filter->Init.InjectedParam.Trigger;
hdfsdm_filter->ExtTriggerEdge = hdfsdm_filter->Init.InjectedParam.ExtTriggerEdge;
hdfsdm_filter->InjectedScanMode = hdfsdm_filter->Init.InjectedParam.ScanMode;
hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_DFEN;
hdfsdm_filter->State = HAL_DFSDM_FILTER_STATE_READY;
return HAL_OK;
}HAL_DFSDM_FilterInit (DFSDM_Filter_HandleTypeDef *hdfsdm_filter) { ... }
/* ... */
HAL_StatusTypeDef HAL_DFSDM_FilterDeInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
{
if(hdfsdm_filter == NULL)
{
return HAL_ERROR;
}if (hdfsdm_filter == NULL) { ... }
assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_DFEN);
#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
if(hdfsdm_filter->MspDeInitCallback == NULL)
{
hdfsdm_filter->MspDeInitCallback = HAL_DFSDM_FilterMspDeInit;
}if (hdfsdm_filter->MspDeInitCallback == NULL) { ... }
hdfsdm_filter->MspDeInitCallback(hdfsdm_filter);/* ... */
#else
HAL_DFSDM_FilterMspDeInit(hdfsdm_filter);
#endif
hdfsdm_filter->State = HAL_DFSDM_FILTER_STATE_RESET;
return HAL_OK;
}HAL_DFSDM_FilterDeInit (DFSDM_Filter_HandleTypeDef *hdfsdm_filter) { ... }
/* ... */
__weak void HAL_DFSDM_FilterMspInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
{
UNUSED(hdfsdm_filter);
/* ... */
}HAL_DFSDM_FilterMspInit (DFSDM_Filter_HandleTypeDef *hdfsdm_filter) { ... }
/* ... */
__weak void HAL_DFSDM_FilterMspDeInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
{
UNUSED(hdfsdm_filter);
/* ... */
}HAL_DFSDM_FilterMspDeInit (DFSDM_Filter_HandleTypeDef *hdfsdm_filter) { ... }
#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
/* ... */
HAL_StatusTypeDef HAL_DFSDM_Filter_RegisterCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
HAL_DFSDM_Filter_CallbackIDTypeDef CallbackID,
pDFSDM_Filter_CallbackTypeDef pCallback)
{
HAL_StatusTypeDef status = HAL_OK;
if(pCallback == NULL)
{
hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_INVALID_CALLBACK;
status = HAL_ERROR;
}if (pCallback == NULL) { ... }
else
{
if(HAL_DFSDM_FILTER_STATE_READY == hdfsdm_filter->State)
{
switch (CallbackID)
{
case HAL_DFSDM_FILTER_REGCONV_COMPLETE_CB_ID :
hdfsdm_filter->RegConvCpltCallback = pCallback;
break;case HAL_DFSDM_FILTER_REGCONV_COMPLETE_CB_ID :
case HAL_DFSDM_FILTER_REGCONV_HALFCOMPLETE_CB_ID :
hdfsdm_filter->RegConvHalfCpltCallback = pCallback;
break;case HAL_DFSDM_FILTER_REGCONV_HALFCOMPLETE_CB_ID :
case HAL_DFSDM_FILTER_INJCONV_COMPLETE_CB_ID :
hdfsdm_filter->InjConvCpltCallback = pCallback;
break;case HAL_DFSDM_FILTER_INJCONV_COMPLETE_CB_ID :
case HAL_DFSDM_FILTER_INJCONV_HALFCOMPLETE_CB_ID :
hdfsdm_filter->InjConvHalfCpltCallback = pCallback;
break;case HAL_DFSDM_FILTER_INJCONV_HALFCOMPLETE_CB_ID :
case HAL_DFSDM_FILTER_ERROR_CB_ID :
hdfsdm_filter->ErrorCallback = pCallback;
break;case HAL_DFSDM_FILTER_ERROR_CB_ID :
case HAL_DFSDM_FILTER_MSPINIT_CB_ID :
hdfsdm_filter->MspInitCallback = pCallback;
break;case HAL_DFSDM_FILTER_MSPINIT_CB_ID :
case HAL_DFSDM_FILTER_MSPDEINIT_CB_ID :
hdfsdm_filter->MspDeInitCallback = pCallback;
break;case HAL_DFSDM_FILTER_MSPDEINIT_CB_ID :
default :
hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_INVALID_CALLBACK;
status = HAL_ERROR;
break;default
}switch (CallbackID) { ... }
}if (HAL_DFSDM_FILTER_STATE_READY == hdfsdm_filter->State) { ... }
else if(HAL_DFSDM_FILTER_STATE_RESET == hdfsdm_filter->State)
{
switch (CallbackID)
{
case HAL_DFSDM_FILTER_MSPINIT_CB_ID :
hdfsdm_filter->MspInitCallback = pCallback;
break;case HAL_DFSDM_FILTER_MSPINIT_CB_ID :
case HAL_DFSDM_FILTER_MSPDEINIT_CB_ID :
hdfsdm_filter->MspDeInitCallback = pCallback;
break;case HAL_DFSDM_FILTER_MSPDEINIT_CB_ID :
default :
hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_INVALID_CALLBACK;
status = HAL_ERROR;
break;default
}switch (CallbackID) { ... }
}else if (HAL_DFSDM_FILTER_STATE_RESET == hdfsdm_filter->State) { ... }
else
{
hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_INVALID_CALLBACK;
status = HAL_ERROR;
}else { ... }
}else { ... }
return status;
}HAL_DFSDM_Filter_RegisterCallback (DFSDM_Filter_HandleTypeDef *hdfsdm_filter, HAL_DFSDM_Filter_CallbackIDTypeDef CallbackID, pDFSDM_Filter_CallbackTypeDef pCallback) { ... }
/* ... */
HAL_StatusTypeDef HAL_DFSDM_Filter_UnRegisterCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
HAL_DFSDM_Filter_CallbackIDTypeDef CallbackID)
{
HAL_StatusTypeDef status = HAL_OK;
if(HAL_DFSDM_FILTER_STATE_READY == hdfsdm_filter->State)
{
switch (CallbackID)
{
case HAL_DFSDM_FILTER_REGCONV_COMPLETE_CB_ID :
hdfsdm_filter->RegConvCpltCallback = HAL_DFSDM_FilterRegConvCpltCallback;
break;case HAL_DFSDM_FILTER_REGCONV_COMPLETE_CB_ID :
case HAL_DFSDM_FILTER_REGCONV_HALFCOMPLETE_CB_ID :
hdfsdm_filter->RegConvHalfCpltCallback = HAL_DFSDM_FilterRegConvHalfCpltCallback;
break;case HAL_DFSDM_FILTER_REGCONV_HALFCOMPLETE_CB_ID :
case HAL_DFSDM_FILTER_INJCONV_COMPLETE_CB_ID :
hdfsdm_filter->InjConvCpltCallback = HAL_DFSDM_FilterInjConvCpltCallback;
break;case HAL_DFSDM_FILTER_INJCONV_COMPLETE_CB_ID :
case HAL_DFSDM_FILTER_INJCONV_HALFCOMPLETE_CB_ID :
hdfsdm_filter->InjConvHalfCpltCallback = HAL_DFSDM_FilterInjConvHalfCpltCallback;
break;case HAL_DFSDM_FILTER_INJCONV_HALFCOMPLETE_CB_ID :
case HAL_DFSDM_FILTER_ERROR_CB_ID :
hdfsdm_filter->ErrorCallback = HAL_DFSDM_FilterErrorCallback;
break;case HAL_DFSDM_FILTER_ERROR_CB_ID :
case HAL_DFSDM_FILTER_MSPINIT_CB_ID :
hdfsdm_filter->MspInitCallback = HAL_DFSDM_FilterMspInit;
break;case HAL_DFSDM_FILTER_MSPINIT_CB_ID :
case HAL_DFSDM_FILTER_MSPDEINIT_CB_ID :
hdfsdm_filter->MspDeInitCallback = HAL_DFSDM_FilterMspDeInit;
break;case HAL_DFSDM_FILTER_MSPDEINIT_CB_ID :
default :
hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_INVALID_CALLBACK;
status = HAL_ERROR;
break;default
}switch (CallbackID) { ... }
}if (HAL_DFSDM_FILTER_STATE_READY == hdfsdm_filter->State) { ... }
else if(HAL_DFSDM_FILTER_STATE_RESET == hdfsdm_filter->State)
{
switch (CallbackID)
{
case HAL_DFSDM_FILTER_MSPINIT_CB_ID :
hdfsdm_filter->MspInitCallback = HAL_DFSDM_FilterMspInit;
break;case HAL_DFSDM_FILTER_MSPINIT_CB_ID :
case HAL_DFSDM_FILTER_MSPDEINIT_CB_ID :
hdfsdm_filter->MspDeInitCallback = HAL_DFSDM_FilterMspDeInit;
break;case HAL_DFSDM_FILTER_MSPDEINIT_CB_ID :
default :
hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_INVALID_CALLBACK;
status = HAL_ERROR;
break;default
}switch (CallbackID) { ... }
}else if (HAL_DFSDM_FILTER_STATE_RESET == hdfsdm_filter->State) { ... }
else
{
hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_INVALID_CALLBACK;
status = HAL_ERROR;
}else { ... }
return status;
}HAL_DFSDM_Filter_UnRegisterCallback (DFSDM_Filter_HandleTypeDef *hdfsdm_filter, HAL_DFSDM_Filter_CallbackIDTypeDef CallbackID) { ... }
/* ... */
HAL_StatusTypeDef HAL_DFSDM_Filter_RegisterAwdCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
pDFSDM_Filter_AwdCallbackTypeDef pCallback)
{
HAL_StatusTypeDef status = HAL_OK;
if(pCallback == NULL)
{
hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_INVALID_CALLBACK;
status = HAL_ERROR;
}if (pCallback == NULL) { ... }
else
{
if(HAL_DFSDM_FILTER_STATE_READY == hdfsdm_filter->State)
{
hdfsdm_filter->AwdCallback = pCallback;
}if (HAL_DFSDM_FILTER_STATE_READY == hdfsdm_filter->State) { ... }
else
{
hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_INVALID_CALLBACK;
status = HAL_ERROR;
}else { ... }
}else { ... }
return status;
}HAL_DFSDM_Filter_RegisterAwdCallback (DFSDM_Filter_HandleTypeDef *hdfsdm_filter, pDFSDM_Filter_AwdCallbackTypeDef pCallback) { ... }
/* ... */
HAL_StatusTypeDef HAL_DFSDM_Filter_UnRegisterAwdCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
{
HAL_StatusTypeDef status = HAL_OK;
if(HAL_DFSDM_FILTER_STATE_READY == hdfsdm_filter->State)
{
hdfsdm_filter->AwdCallback = HAL_DFSDM_FilterAwdCallback;
}if (HAL_DFSDM_FILTER_STATE_READY == hdfsdm_filter->State) { ... }
else
{
hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_INVALID_CALLBACK;
status = HAL_ERROR;
}else { ... }
return status;
}HAL_DFSDM_Filter_UnRegisterAwdCallback (DFSDM_Filter_HandleTypeDef *hdfsdm_filter) { ... }
/* ... */#endif
/* ... */
/* ... */
/* ... */
HAL_StatusTypeDef HAL_DFSDM_FilterConfigRegChannel(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
uint32_t Channel,
uint32_t ContinuousMode)
{
HAL_StatusTypeDef status = HAL_OK;
assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
assert_param(IS_DFSDM_REGULAR_CHANNEL(Channel));
assert_param(IS_DFSDM_CONTINUOUS_MODE(ContinuousMode));
if((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_RESET) &&
(hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_ERROR))
{
hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_RCH | DFSDM_FLTCR1_RCONT);
if(ContinuousMode == DFSDM_CONTINUOUS_CONV_ON)
{
hdfsdm_filter->Instance->FLTCR1 |= (uint32_t) (((Channel & DFSDM_MSB_MASK) << DFSDM_FLTCR1_MSB_RCH_OFFSET) |
DFSDM_FLTCR1_RCONT);
}if (ContinuousMode == DFSDM_CONTINUOUS_CONV_ON) { ... }
else
{
hdfsdm_filter->Instance->FLTCR1 |= (uint32_t) ((Channel & DFSDM_MSB_MASK) << DFSDM_FLTCR1_MSB_RCH_OFFSET);
}else { ... }
hdfsdm_filter->RegularContMode = ContinuousMode;
}if ((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_RESET) && (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_ERROR)) { ... }
else
{
status = HAL_ERROR;
}else { ... }
return status;
}HAL_DFSDM_FilterConfigRegChannel (DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Channel, uint32_t ContinuousMode) { ... }
/* ... */
HAL_StatusTypeDef HAL_DFSDM_FilterConfigInjChannel(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
uint32_t Channel)
{
HAL_StatusTypeDef status = HAL_OK;
assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
assert_param(IS_DFSDM_INJECTED_CHANNEL(Channel));
if((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_RESET) &&
(hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_ERROR))
{
hdfsdm_filter->Instance->FLTJCHGR = (uint32_t) (Channel & DFSDM_LSB_MASK);
hdfsdm_filter->InjectedChannelsNbr = DFSDM_GetInjChannelsNbr(Channel);
hdfsdm_filter->InjConvRemaining = (hdfsdm_filter->InjectedScanMode == ENABLE) ? \
hdfsdm_filter->InjectedChannelsNbr : 1U;
}if ((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_RESET) && (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_ERROR)) { ... }
else
{
status = HAL_ERROR;
}else { ... }
return status;
}HAL_DFSDM_FilterConfigInjChannel (DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Channel) { ... }
/* ... */
/* ... */
/* ... */
HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
{
HAL_StatusTypeDef status = HAL_OK;
assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) || \
(hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_INJ))
{
DFSDM_RegConvStart(hdfsdm_filter);
}if ((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) || \ (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_INJ)) { ... }
else
{
status = HAL_ERROR;
}else { ... }
return status;
}HAL_DFSDM_FilterRegularStart (DFSDM_Filter_HandleTypeDef *hdfsdm_filter) { ... }
/* ... */
HAL_StatusTypeDef HAL_DFSDM_FilterPollForRegConversion(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
uint32_t Timeout)
{
uint32_t tickstart;
assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
if((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG) && \
(hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG_INJ))
{
return HAL_ERROR;
}if ((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG) && \ (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG_INJ)) { ... }
else
{
tickstart = HAL_GetTick();
while((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_REOCF) != DFSDM_FLTISR_REOCF)
{
if(Timeout != HAL_MAX_DELAY)
{
if(((HAL_GetTick()-tickstart) > Timeout) || (Timeout == 0U))
{
return HAL_TIMEOUT;
}if (((HAL_GetTick()-tickstart) > Timeout) || (Timeout == 0U)) { ... }
}if (Timeout != HAL_MAX_DELAY) { ... }
}while ((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_REOCF) != DFSDM_FLTISR_REOCF) { ... }
if((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_ROVRF) == DFSDM_FLTISR_ROVRF)
{
hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_REGULAR_OVERRUN;
#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
hdfsdm_filter->ErrorCallback(hdfsdm_filter);
#else
HAL_DFSDM_FilterErrorCallback(hdfsdm_filter);
#endif
hdfsdm_filter->Instance->FLTICR = DFSDM_FLTICR_CLRROVRF;
}if ((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_ROVRF) == DFSDM_FLTISR_ROVRF) { ... }
if((hdfsdm_filter->RegularContMode == DFSDM_CONTINUOUS_CONV_OFF) && \
(hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SW_TRIGGER))
{
hdfsdm_filter->State = (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG) ? \
HAL_DFSDM_FILTER_STATE_READY : HAL_DFSDM_FILTER_STATE_INJ;
}if ((hdfsdm_filter->RegularContMode == DFSDM_CONTINUOUS_CONV_OFF) && \ (hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SW_TRIGGER)) { ... }
return HAL_OK;
}else { ... }
}HAL_DFSDM_FilterPollForRegConversion (DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Timeout) { ... }
/* ... */
HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
{
HAL_StatusTypeDef status = HAL_OK;
assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
if((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG) && \
(hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG_INJ))
{
status = HAL_ERROR;
}if ((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG) && \ (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG_INJ)) { ... }
else
{
DFSDM_RegConvStop(hdfsdm_filter);
}else { ... }
return status;
}HAL_DFSDM_FilterRegularStop (DFSDM_Filter_HandleTypeDef *hdfsdm_filter) { ... }
/* ... */
HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
{
HAL_StatusTypeDef status = HAL_OK;
assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) || \
(hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_INJ))
{
hdfsdm_filter->Instance->FLTCR2 |= (DFSDM_FLTCR2_REOCIE | DFSDM_FLTCR2_ROVRIE);
DFSDM_RegConvStart(hdfsdm_filter);
}if ((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) || \ (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_INJ)) { ... }
else
{
status = HAL_ERROR;
}else { ... }
return status;
}HAL_DFSDM_FilterRegularStart_IT (DFSDM_Filter_HandleTypeDef *hdfsdm_filter) { ... }
/* ... */
HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
{
HAL_StatusTypeDef status = HAL_OK;
assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
if((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG) && \
(hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG_INJ))
{
status = HAL_ERROR;
}if ((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG) && \ (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG_INJ)) { ... }
else
{
hdfsdm_filter->Instance->FLTCR2 &= ~(DFSDM_FLTCR2_REOCIE | DFSDM_FLTCR2_ROVRIE);
DFSDM_RegConvStop(hdfsdm_filter);
}else { ... }
return status;
}HAL_DFSDM_FilterRegularStop_IT (DFSDM_Filter_HandleTypeDef *hdfsdm_filter) { ... }
/* ... */
HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
int32_t *pData,
uint32_t Length)
{
HAL_StatusTypeDef status = HAL_OK;
assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
if((pData == NULL) || (Length == 0U))
{
status = HAL_ERROR;
}if ((pData == NULL) || (Length == 0U)) { ... }
else if((hdfsdm_filter->Instance->FLTCR1 & DFSDM_FLTCR1_RDMAEN) != DFSDM_FLTCR1_RDMAEN)
{
status = HAL_ERROR;
}else if ((hdfsdm_filter->Instance->FLTCR1 & DFSDM_FLTCR1_RDMAEN) != DFSDM_FLTCR1_RDMAEN) { ... }
else if((hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SW_TRIGGER) && \
(hdfsdm_filter->RegularContMode == DFSDM_CONTINUOUS_CONV_OFF) && \
(hdfsdm_filter->hdmaReg->Init.Mode == DMA_NORMAL) && \
(Length != 1U))
{
status = HAL_ERROR;
}else if ((hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SW_TRIGGER) && \ (hdfsdm_filter->RegularContMode == DFSDM_CONTINUOUS_CONV_OFF) && \ (hdfsdm_filter->hdmaReg->Init.Mode == DMA_NORMAL) && \ (Length != 1U)) { ... }
else if((hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SW_TRIGGER) && \
(hdfsdm_filter->RegularContMode == DFSDM_CONTINUOUS_CONV_OFF) && \
(hdfsdm_filter->hdmaReg->Init.Mode == DMA_CIRCULAR))
{
status = HAL_ERROR;
}else if ((hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SW_TRIGGER) && \ (hdfsdm_filter->RegularContMode == DFSDM_CONTINUOUS_CONV_OFF) && \ (hdfsdm_filter->hdmaReg->Init.Mode == DMA_CIRCULAR)) { ... }
else if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) || \
(hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_INJ))
{
hdfsdm_filter->hdmaReg->XferCpltCallback = DFSDM_DMARegularConvCplt;
hdfsdm_filter->hdmaReg->XferErrorCallback = DFSDM_DMAError;
hdfsdm_filter->hdmaReg->XferHalfCpltCallback = (hdfsdm_filter->hdmaReg->Init.Mode == DMA_CIRCULAR) ?\
DFSDM_DMARegularHalfConvCplt : NULL;
if(HAL_DMA_Start_IT(hdfsdm_filter->hdmaReg, (uint32_t)&hdfsdm_filter->Instance->FLTRDATAR, \
(uint32_t) pData, Length) != HAL_OK)
{
hdfsdm_filter->State = HAL_DFSDM_FILTER_STATE_ERROR;
status = HAL_ERROR;
}if (HAL_DMA_Start_IT(hdfsdm_filter->hdmaReg, (uint32_t)&hdfsdm_filter->Instance->FLTRDATAR, \ (uint32_t) pData, Length) != HAL_OK) { ... }
else
{
DFSDM_RegConvStart(hdfsdm_filter);
}else { ... }
}else if ((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) || \ (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_INJ)) { ... }
else
{
status = HAL_ERROR;
}else { ... }
return status;
}HAL_DFSDM_FilterRegularStart_DMA (DFSDM_Filter_HandleTypeDef *hdfsdm_filter, int32_t *pData, uint32_t Length) { ... }
/* ... */
HAL_StatusTypeDef HAL_DFSDM_FilterRegularMsbStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
int16_t *pData,
uint32_t Length)
{
HAL_StatusTypeDef status = HAL_OK;
assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
if((pData == NULL) || (Length == 0U))
{
status = HAL_ERROR;
}if ((pData == NULL) || (Length == 0U)) { ... }
else if((hdfsdm_filter->Instance->FLTCR1 & DFSDM_FLTCR1_RDMAEN) != DFSDM_FLTCR1_RDMAEN)
{
status = HAL_ERROR;
}else if ((hdfsdm_filter->Instance->FLTCR1 & DFSDM_FLTCR1_RDMAEN) != DFSDM_FLTCR1_RDMAEN) { ... }
else if((hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SW_TRIGGER) && \
(hdfsdm_filter->RegularContMode == DFSDM_CONTINUOUS_CONV_OFF) && \
(hdfsdm_filter->hdmaReg->Init.Mode == DMA_NORMAL) && \
(Length != 1U))
{
status = HAL_ERROR;
}else if ((hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SW_TRIGGER) && \ (hdfsdm_filter->RegularContMode == DFSDM_CONTINUOUS_CONV_OFF) && \ (hdfsdm_filter->hdmaReg->Init.Mode == DMA_NORMAL) && \ (Length != 1U)) { ... }
else if((hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SW_TRIGGER) && \
(hdfsdm_filter->RegularContMode == DFSDM_CONTINUOUS_CONV_OFF) && \
(hdfsdm_filter->hdmaReg->Init.Mode == DMA_CIRCULAR))
{
status = HAL_ERROR;
}else if ((hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SW_TRIGGER) && \ (hdfsdm_filter->RegularContMode == DFSDM_CONTINUOUS_CONV_OFF) && \ (hdfsdm_filter->hdmaReg->Init.Mode == DMA_CIRCULAR)) { ... }
else if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) || \
(hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_INJ))
{
hdfsdm_filter->hdmaReg->XferCpltCallback = DFSDM_DMARegularConvCplt;
hdfsdm_filter->hdmaReg->XferErrorCallback = DFSDM_DMAError;
hdfsdm_filter->hdmaReg->XferHalfCpltCallback = (hdfsdm_filter->hdmaReg->Init.Mode == DMA_CIRCULAR) ?\
DFSDM_DMARegularHalfConvCplt : NULL;
if(HAL_DMA_Start_IT(hdfsdm_filter->hdmaReg, (uint32_t)(&hdfsdm_filter->Instance->FLTRDATAR) + 2U, \
(uint32_t) pData, Length) != HAL_OK)
{
hdfsdm_filter->State = HAL_DFSDM_FILTER_STATE_ERROR;
status = HAL_ERROR;
}if (HAL_DMA_Start_IT(hdfsdm_filter->hdmaReg, (uint32_t)(&hdfsdm_filter->Instance->FLTRDATAR) + 2U, \ (uint32_t) pData, Length) != HAL_OK) { ... }
else
{
DFSDM_RegConvStart(hdfsdm_filter);
}else { ... }
}else if ((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) || \ (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_INJ)) { ... }
else
{
status = HAL_ERROR;
}else { ... }
return status;
}HAL_DFSDM_FilterRegularMsbStart_DMA (DFSDM_Filter_HandleTypeDef *hdfsdm_filter, int16_t *pData, uint32_t Length) { ... }
/* ... */
HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
{
HAL_StatusTypeDef status = HAL_OK;
assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
if((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG) && \
(hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG_INJ))
{
status = HAL_ERROR;
}if ((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG) && \ (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG_INJ)) { ... }
else
{
if(HAL_DMA_Abort(hdfsdm_filter->hdmaReg) != HAL_OK)
{
hdfsdm_filter->State = HAL_DFSDM_FILTER_STATE_ERROR;
status = HAL_ERROR;
}if (HAL_DMA_Abort(hdfsdm_filter->hdmaReg) != HAL_OK) { ... }
else
{
DFSDM_RegConvStop(hdfsdm_filter);
}else { ... }
}else { ... }
return status;
}HAL_DFSDM_FilterRegularStop_DMA (DFSDM_Filter_HandleTypeDef *hdfsdm_filter) { ... }
/* ... */
int32_t HAL_DFSDM_FilterGetRegularValue(const DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
uint32_t *Channel)
{
uint32_t reg = 0U;
int32_t value = 0;
assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
assert_param(Channel != NULL);
reg = hdfsdm_filter->Instance->FLTRDATAR;
*Channel = (reg & DFSDM_FLTRDATAR_RDATACH);
value = ((int32_t)(reg & DFSDM_FLTRDATAR_RDATA) >> DFSDM_FLTRDATAR_RDATA_Pos);
return value;
}HAL_DFSDM_FilterGetRegularValue (const DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t *Channel) { ... }
/* ... */
HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
{
HAL_StatusTypeDef status = HAL_OK;
assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) || \
(hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG))
{
DFSDM_InjConvStart(hdfsdm_filter);
}if ((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) || \ (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG)) { ... }
else
{
status = HAL_ERROR;
}else { ... }
return status;
}HAL_DFSDM_FilterInjectedStart (DFSDM_Filter_HandleTypeDef *hdfsdm_filter) { ... }
/* ... */
HAL_StatusTypeDef HAL_DFSDM_FilterPollForInjConversion(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
uint32_t Timeout)
{
uint32_t tickstart;
assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
if((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_INJ) && \
(hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG_INJ))
{
return HAL_ERROR;
}if ((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_INJ) && \ (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG_INJ)) { ... }
else
{
tickstart = HAL_GetTick();
while((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_JEOCF) != DFSDM_FLTISR_JEOCF)
{
if(Timeout != HAL_MAX_DELAY)
{
if( ((HAL_GetTick()-tickstart) > Timeout) || (Timeout == 0U))
{
return HAL_TIMEOUT;
}if (((HAL_GetTick()-tickstart) > Timeout) || (Timeout == 0U)) { ... }
}if (Timeout != HAL_MAX_DELAY) { ... }
}while ((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_JEOCF) != DFSDM_FLTISR_JEOCF) { ... }
if((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_JOVRF) == DFSDM_FLTISR_JOVRF)
{
hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_INJECTED_OVERRUN;
#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
hdfsdm_filter->ErrorCallback(hdfsdm_filter);
#else
HAL_DFSDM_FilterErrorCallback(hdfsdm_filter);
#endif
hdfsdm_filter->Instance->FLTICR = DFSDM_FLTICR_CLRJOVRF;
}if ((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_JOVRF) == DFSDM_FLTISR_JOVRF) { ... }
hdfsdm_filter->InjConvRemaining--;
if(hdfsdm_filter->InjConvRemaining == 0U)
{
if(hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SW_TRIGGER)
{
hdfsdm_filter->State = (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_INJ) ? \
HAL_DFSDM_FILTER_STATE_READY : HAL_DFSDM_FILTER_STATE_REG;
}if (hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SW_TRIGGER) { ... }
hdfsdm_filter->InjConvRemaining = (hdfsdm_filter->InjectedScanMode == ENABLE) ? \
hdfsdm_filter->InjectedChannelsNbr : 1U;
}if (hdfsdm_filter->InjConvRemaining == 0U) { ... }
return HAL_OK;
}else { ... }
}HAL_DFSDM_FilterPollForInjConversion (DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Timeout) { ... }
/* ... */
HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
{
HAL_StatusTypeDef status = HAL_OK;
assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
if((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_INJ) && \
(hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG_INJ))
{
status = HAL_ERROR;
}if ((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_INJ) && \ (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG_INJ)) { ... }
else
{
DFSDM_InjConvStop(hdfsdm_filter);
}else { ... }
return status;
}HAL_DFSDM_FilterInjectedStop (DFSDM_Filter_HandleTypeDef *hdfsdm_filter) { ... }
/* ... */
HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
{
HAL_StatusTypeDef status = HAL_OK;
assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) || \
(hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG))
{
hdfsdm_filter->Instance->FLTCR2 |= (DFSDM_FLTCR2_JEOCIE | DFSDM_FLTCR2_JOVRIE);
DFSDM_InjConvStart(hdfsdm_filter);
}if ((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) || \ (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG)) { ... }
else
{
status = HAL_ERROR;
}else { ... }
return status;
}HAL_DFSDM_FilterInjectedStart_IT (DFSDM_Filter_HandleTypeDef *hdfsdm_filter) { ... }
/* ... */
HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
{
HAL_StatusTypeDef status = HAL_OK;
assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
if((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_INJ) && \
(hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG_INJ))
{
status = HAL_ERROR;
}if ((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_INJ) && \ (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG_INJ)) { ... }
else
{
hdfsdm_filter->Instance->FLTCR2 &= ~(DFSDM_FLTCR2_JEOCIE | DFSDM_FLTCR2_JOVRIE);
DFSDM_InjConvStop(hdfsdm_filter);
}else { ... }
return status;
}HAL_DFSDM_FilterInjectedStop_IT (DFSDM_Filter_HandleTypeDef *hdfsdm_filter) { ... }
/* ... */
HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
int32_t *pData,
uint32_t Length)
{
HAL_StatusTypeDef status = HAL_OK;
assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
if((pData == NULL) || (Length == 0U))
{
status = HAL_ERROR;
}if ((pData == NULL) || (Length == 0U)) { ... }
else if((hdfsdm_filter->Instance->FLTCR1 & DFSDM_FLTCR1_JDMAEN) != DFSDM_FLTCR1_JDMAEN)
{
status = HAL_ERROR;
}else if ((hdfsdm_filter->Instance->FLTCR1 & DFSDM_FLTCR1_JDMAEN) != DFSDM_FLTCR1_JDMAEN) { ... }
else if((hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SW_TRIGGER) && \
(hdfsdm_filter->hdmaInj->Init.Mode == DMA_NORMAL) && \
(Length > hdfsdm_filter->InjConvRemaining))
{
status = HAL_ERROR;
}else if ((hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SW_TRIGGER) && \ (hdfsdm_filter->hdmaInj->Init.Mode == DMA_NORMAL) && \ (Length > hdfsdm_filter->InjConvRemaining)) { ... }
else if((hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SW_TRIGGER) && \
(hdfsdm_filter->hdmaInj->Init.Mode == DMA_CIRCULAR))
{
status = HAL_ERROR;
}else if ((hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SW_TRIGGER) && \ (hdfsdm_filter->hdmaInj->Init.Mode == DMA_CIRCULAR)) { ... }
else if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) || \
(hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG))
{
hdfsdm_filter->hdmaInj->XferCpltCallback = DFSDM_DMAInjectedConvCplt;
hdfsdm_filter->hdmaInj->XferErrorCallback = DFSDM_DMAError;
hdfsdm_filter->hdmaInj->XferHalfCpltCallback = (hdfsdm_filter->hdmaInj->Init.Mode == DMA_CIRCULAR) ?\
DFSDM_DMAInjectedHalfConvCplt : NULL;
if(HAL_DMA_Start_IT(hdfsdm_filter->hdmaInj, (uint32_t)&hdfsdm_filter->Instance->FLTJDATAR, \
(uint32_t) pData, Length) != HAL_OK)
{
hdfsdm_filter->State = HAL_DFSDM_FILTER_STATE_ERROR;
status = HAL_ERROR;
}if (HAL_DMA_Start_IT(hdfsdm_filter->hdmaInj, (uint32_t)&hdfsdm_filter->Instance->FLTJDATAR, \ (uint32_t) pData, Length) != HAL_OK) { ... }
else
{
DFSDM_InjConvStart(hdfsdm_filter);
}else { ... }
}else if ((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) || \ (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG)) { ... }
else
{
status = HAL_ERROR;
}else { ... }
return status;
}HAL_DFSDM_FilterInjectedStart_DMA (DFSDM_Filter_HandleTypeDef *hdfsdm_filter, int32_t *pData, uint32_t Length) { ... }
/* ... */
HAL_StatusTypeDef HAL_DFSDM_FilterInjectedMsbStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
int16_t *pData,
uint32_t Length)
{
HAL_StatusTypeDef status = HAL_OK;
assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
if((pData == NULL) || (Length == 0U))
{
status = HAL_ERROR;
}if ((pData == NULL) || (Length == 0U)) { ... }
else if((hdfsdm_filter->Instance->FLTCR1 & DFSDM_FLTCR1_JDMAEN) != DFSDM_FLTCR1_JDMAEN)
{
status = HAL_ERROR;
}else if ((hdfsdm_filter->Instance->FLTCR1 & DFSDM_FLTCR1_JDMAEN) != DFSDM_FLTCR1_JDMAEN) { ... }
else if((hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SW_TRIGGER) && \
(hdfsdm_filter->hdmaInj->Init.Mode == DMA_NORMAL) && \
(Length > hdfsdm_filter->InjConvRemaining))
{
status = HAL_ERROR;
}else if ((hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SW_TRIGGER) && \ (hdfsdm_filter->hdmaInj->Init.Mode == DMA_NORMAL) && \ (Length > hdfsdm_filter->InjConvRemaining)) { ... }
else if((hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SW_TRIGGER) && \
(hdfsdm_filter->hdmaInj->Init.Mode == DMA_CIRCULAR))
{
status = HAL_ERROR;
}else if ((hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SW_TRIGGER) && \ (hdfsdm_filter->hdmaInj->Init.Mode == DMA_CIRCULAR)) { ... }
else if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) || \
(hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG))
{
hdfsdm_filter->hdmaInj->XferCpltCallback = DFSDM_DMAInjectedConvCplt;
hdfsdm_filter->hdmaInj->XferErrorCallback = DFSDM_DMAError;
hdfsdm_filter->hdmaInj->XferHalfCpltCallback = (hdfsdm_filter->hdmaInj->Init.Mode == DMA_CIRCULAR) ?\
DFSDM_DMAInjectedHalfConvCplt : NULL;
if(HAL_DMA_Start_IT(hdfsdm_filter->hdmaInj, (uint32_t)(&hdfsdm_filter->Instance->FLTJDATAR) + 2U, \
(uint32_t) pData, Length) != HAL_OK)
{
hdfsdm_filter->State = HAL_DFSDM_FILTER_STATE_ERROR;
status = HAL_ERROR;
}if (HAL_DMA_Start_IT(hdfsdm_filter->hdmaInj, (uint32_t)(&hdfsdm_filter->Instance->FLTJDATAR) + 2U, \ (uint32_t) pData, Length) != HAL_OK) { ... }
else
{
DFSDM_InjConvStart(hdfsdm_filter);
}else { ... }
}else if ((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) || \ (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG)) { ... }
else
{
status = HAL_ERROR;
}else { ... }
return status;
}HAL_DFSDM_FilterInjectedMsbStart_DMA (DFSDM_Filter_HandleTypeDef *hdfsdm_filter, int16_t *pData, uint32_t Length) { ... }
/* ... */
HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
{
HAL_StatusTypeDef status = HAL_OK;
assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
if((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_INJ) && \
(hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG_INJ))
{
status = HAL_ERROR;
}if ((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_INJ) && \ (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG_INJ)) { ... }
else
{
if(HAL_DMA_Abort(hdfsdm_filter->hdmaInj) != HAL_OK)
{
hdfsdm_filter->State = HAL_DFSDM_FILTER_STATE_ERROR;
status = HAL_ERROR;
}if (HAL_DMA_Abort(hdfsdm_filter->hdmaInj) != HAL_OK) { ... }
else
{
DFSDM_InjConvStop(hdfsdm_filter);
}else { ... }
}else { ... }
return status;
}HAL_DFSDM_FilterInjectedStop_DMA (DFSDM_Filter_HandleTypeDef *hdfsdm_filter) { ... }
/* ... */
int32_t HAL_DFSDM_FilterGetInjectedValue(const DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
uint32_t *Channel)
{
uint32_t reg = 0U;
int32_t value = 0;
assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
assert_param(Channel != NULL);
reg = hdfsdm_filter->Instance->FLTJDATAR;
*Channel = (reg & DFSDM_FLTJDATAR_JDATACH);
value = ((int32_t)(reg & DFSDM_FLTJDATAR_JDATA) >> DFSDM_FLTJDATAR_JDATA_Pos);
return value;
}HAL_DFSDM_FilterGetInjectedValue (const DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t *Channel) { ... }
/* ... */
HAL_StatusTypeDef HAL_DFSDM_FilterAwdStart_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
const DFSDM_Filter_AwdParamTypeDef *awdParam)
{
HAL_StatusTypeDef status = HAL_OK;
assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
assert_param(IS_DFSDM_FILTER_AWD_DATA_SOURCE(awdParam->DataSource));
assert_param(IS_DFSDM_INJECTED_CHANNEL(awdParam->Channel));
assert_param(IS_DFSDM_FILTER_AWD_THRESHOLD(awdParam->HighThreshold));
assert_param(IS_DFSDM_FILTER_AWD_THRESHOLD(awdParam->LowThreshold));
assert_param(IS_DFSDM_BREAK_SIGNALS(awdParam->HighBreakSignal));
assert_param(IS_DFSDM_BREAK_SIGNALS(awdParam->LowBreakSignal));
if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_RESET) || \
(hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_ERROR))
{
status = HAL_ERROR;
}if ((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_RESET) || \ (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_ERROR)) { ... }
else
{
hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_AWFSEL);
hdfsdm_filter->Instance->FLTCR1 |= awdParam->DataSource;
hdfsdm_filter->Instance->FLTAWHTR &= ~(DFSDM_FLTAWHTR_AWHT | DFSDM_FLTAWHTR_BKAWH);
hdfsdm_filter->Instance->FLTAWHTR |= (((uint32_t) awdParam->HighThreshold << DFSDM_FLTAWHTR_AWHT_Pos) | \
awdParam->HighBreakSignal);
hdfsdm_filter->Instance->FLTAWLTR &= ~(DFSDM_FLTAWLTR_AWLT | DFSDM_FLTAWLTR_BKAWL);
hdfsdm_filter->Instance->FLTAWLTR |= (((uint32_t) awdParam->LowThreshold << DFSDM_FLTAWLTR_AWLT_Pos) | \
awdParam->LowBreakSignal);
hdfsdm_filter->Instance->FLTCR2 &= ~(DFSDM_FLTCR2_AWDCH);
hdfsdm_filter->Instance->FLTCR2 |= (((awdParam->Channel & DFSDM_LSB_MASK) << DFSDM_FLTCR2_AWDCH_Pos) | \
DFSDM_FLTCR2_AWDIE);
}else { ... }
return status;
}HAL_DFSDM_FilterAwdStart_IT (DFSDM_Filter_HandleTypeDef *hdfsdm_filter, const DFSDM_Filter_AwdParamTypeDef *awdParam) { ... }
/* ... */
HAL_StatusTypeDef HAL_DFSDM_FilterAwdStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
{
HAL_StatusTypeDef status = HAL_OK;
assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_RESET) || \
(hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_ERROR))
{
status = HAL_ERROR;
}if ((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_RESET) || \ (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_ERROR)) { ... }
else
{
hdfsdm_filter->Instance->FLTCR2 &= ~(DFSDM_FLTCR2_AWDCH | DFSDM_FLTCR2_AWDIE);
hdfsdm_filter->Instance->FLTAWCFR = (DFSDM_FLTAWCFR_CLRAWHTF | DFSDM_FLTAWCFR_CLRAWLTF);
hdfsdm_filter->Instance->FLTAWHTR &= ~(DFSDM_FLTAWHTR_AWHT | DFSDM_FLTAWHTR_BKAWH);
hdfsdm_filter->Instance->FLTAWLTR &= ~(DFSDM_FLTAWLTR_AWLT | DFSDM_FLTAWLTR_BKAWL);
hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_AWFSEL);
}else { ... }
return status;
}HAL_DFSDM_FilterAwdStop_IT (DFSDM_Filter_HandleTypeDef *hdfsdm_filter) { ... }
/* ... */
HAL_StatusTypeDef HAL_DFSDM_FilterExdStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
uint32_t Channel)
{
HAL_StatusTypeDef status = HAL_OK;
assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
assert_param(IS_DFSDM_INJECTED_CHANNEL(Channel));
if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_RESET) || \
(hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_ERROR))
{
status = HAL_ERROR;
}if ((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_RESET) || \ (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_ERROR)) { ... }
else
{
hdfsdm_filter->Instance->FLTCR2 &= ~(DFSDM_FLTCR2_EXCH);
hdfsdm_filter->Instance->FLTCR2 |= ((Channel & DFSDM_LSB_MASK) << DFSDM_FLTCR2_EXCH_Pos);
}else { ... }
return status;
}HAL_DFSDM_FilterExdStart (DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Channel) { ... }
/* ... */
HAL_StatusTypeDef HAL_DFSDM_FilterExdStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
{
HAL_StatusTypeDef status = HAL_OK;
__IO uint32_t reg1;
__IO uint32_t reg2;
assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_RESET) || \
(hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_ERROR))
{
status = HAL_ERROR;
}if ((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_RESET) || \ (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_ERROR)) { ... }
else
{
hdfsdm_filter->Instance->FLTCR2 &= ~(DFSDM_FLTCR2_EXCH);
reg1 = hdfsdm_filter->Instance->FLTEXMAX;
reg2 = hdfsdm_filter->Instance->FLTEXMIN;
UNUSED(reg1);
UNUSED(reg2);
}else { ... }
return status;
}HAL_DFSDM_FilterExdStop (DFSDM_Filter_HandleTypeDef *hdfsdm_filter) { ... }
/* ... */
int32_t HAL_DFSDM_FilterGetExdMaxValue(const DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
uint32_t *Channel)
{
uint32_t reg = 0U;
int32_t value = 0;
assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
assert_param(Channel != NULL);
reg = hdfsdm_filter->Instance->FLTEXMAX;
*Channel = (reg & DFSDM_FLTEXMAX_EXMAXCH);
value = ((int32_t)(reg & DFSDM_FLTEXMAX_EXMAX) >> DFSDM_FLTEXMAX_EXMAX_Pos);
return value;
}HAL_DFSDM_FilterGetExdMaxValue (const DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t *Channel) { ... }
/* ... */
int32_t HAL_DFSDM_FilterGetExdMinValue(const DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
uint32_t *Channel)
{
uint32_t reg = 0U;
int32_t value = 0;
assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
assert_param(Channel != NULL);
reg = hdfsdm_filter->Instance->FLTEXMIN;
*Channel = (reg & DFSDM_FLTEXMIN_EXMINCH);
value = ((int32_t)(reg & DFSDM_FLTEXMIN_EXMIN) >> DFSDM_FLTEXMIN_EXMIN_Pos);
return value;
}HAL_DFSDM_FilterGetExdMinValue (const DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t *Channel) { ... }
/* ... */
uint32_t HAL_DFSDM_FilterGetConvTimeValue(const DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
{
uint32_t reg = 0U;
uint32_t value = 0U;
assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
reg = hdfsdm_filter->Instance->FLTCNVTIMR;
value = ((reg & DFSDM_FLTCNVTIMR_CNVCNT) >> DFSDM_FLTCNVTIMR_CNVCNT_Pos);
return value;
}HAL_DFSDM_FilterGetConvTimeValue (const DFSDM_Filter_HandleTypeDef *hdfsdm_filter) { ... }
/* ... */
void HAL_DFSDM_IRQHandler(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
{
if(((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_ROVRF) != 0U) && \
((hdfsdm_filter->Instance->FLTCR2 & DFSDM_FLTCR2_ROVRIE) != 0U))
{
hdfsdm_filter->Instance->FLTICR = DFSDM_FLTICR_CLRROVRF;
hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_REGULAR_OVERRUN;
#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
hdfsdm_filter->ErrorCallback(hdfsdm_filter);
#else
HAL_DFSDM_FilterErrorCallback(hdfsdm_filter);
#endif
}if (((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_ROVRF) != 0U) && \ ((hdfsdm_filter->Instance->FLTCR2 & DFSDM_FLTCR2_ROVRIE) != 0U)) { ... }
else if(((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_JOVRF) != 0U) && \
((hdfsdm_filter->Instance->FLTCR2 & DFSDM_FLTCR2_JOVRIE) != 0U))
{
hdfsdm_filter->Instance->FLTICR = DFSDM_FLTICR_CLRJOVRF;
hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_INJECTED_OVERRUN;
#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
hdfsdm_filter->ErrorCallback(hdfsdm_filter);
#else
HAL_DFSDM_FilterErrorCallback(hdfsdm_filter);
#endif
}else if (((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_JOVRF) != 0U) && \ ((hdfsdm_filter->Instance->FLTCR2 & DFSDM_FLTCR2_JOVRIE) != 0U)) { ... }
else if(((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_REOCF) != 0U) && \
((hdfsdm_filter->Instance->FLTCR2 & DFSDM_FLTCR2_REOCIE) != 0U))
{
#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
hdfsdm_filter->RegConvCpltCallback(hdfsdm_filter);
#else
HAL_DFSDM_FilterRegConvCpltCallback(hdfsdm_filter);
#endif
if((hdfsdm_filter->RegularContMode == DFSDM_CONTINUOUS_CONV_OFF) && \
(hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SW_TRIGGER))
{
hdfsdm_filter->Instance->FLTCR2 &= ~(DFSDM_FLTCR2_REOCIE);
hdfsdm_filter->State = (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG) ? \
HAL_DFSDM_FILTER_STATE_READY : HAL_DFSDM_FILTER_STATE_INJ;
}if ((hdfsdm_filter->RegularContMode == DFSDM_CONTINUOUS_CONV_OFF) && \ (hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SW_TRIGGER)) { ... }
}else if (((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_REOCF) != 0U) && \ ((hdfsdm_filter->Instance->FLTCR2 & DFSDM_FLTCR2_REOCIE) != 0U)) { ... }
else if(((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_JEOCF) != 0U) && \
((hdfsdm_filter->Instance->FLTCR2 & DFSDM_FLTCR2_JEOCIE) != 0U))
{
#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
hdfsdm_filter->InjConvCpltCallback(hdfsdm_filter);
#else
HAL_DFSDM_FilterInjConvCpltCallback(hdfsdm_filter);
#endif
hdfsdm_filter->InjConvRemaining--;
if(hdfsdm_filter->InjConvRemaining == 0U)
{
if(hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SW_TRIGGER)
{
hdfsdm_filter->Instance->FLTCR2 &= ~(DFSDM_FLTCR2_JEOCIE);
hdfsdm_filter->State = (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_INJ) ? \
HAL_DFSDM_FILTER_STATE_READY : HAL_DFSDM_FILTER_STATE_REG;
}if (hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SW_TRIGGER) { ... }
hdfsdm_filter->InjConvRemaining = (hdfsdm_filter->InjectedScanMode == ENABLE) ? \
hdfsdm_filter->InjectedChannelsNbr : 1U;
}if (hdfsdm_filter->InjConvRemaining == 0U) { ... }
}else if (((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_JEOCF) != 0U) && \ ((hdfsdm_filter->Instance->FLTCR2 & DFSDM_FLTCR2_JEOCIE) != 0U)) { ... }
else if(((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_AWDF) != 0U) && \
((hdfsdm_filter->Instance->FLTCR2 & DFSDM_FLTCR2_AWDIE) != 0U))
{
uint32_t reg = 0U;
uint32_t threshold = 0U;
uint32_t channel = 0U;
reg = hdfsdm_filter->Instance->FLTAWSR;
threshold = ((reg & DFSDM_FLTAWSR_AWLTF) != 0U) ? DFSDM_AWD_LOW_THRESHOLD : DFSDM_AWD_HIGH_THRESHOLD;
if(threshold == DFSDM_AWD_HIGH_THRESHOLD)
{
reg = reg >> DFSDM_FLTAWSR_AWHTF_Pos;
}if (threshold == DFSDM_AWD_HIGH_THRESHOLD) { ... }
while((reg & 1U) == 0U)
{
channel++;
reg = reg >> 1U;
}while ((reg & 1U) == 0U) { ... }
hdfsdm_filter->Instance->FLTAWCFR = (threshold == DFSDM_AWD_HIGH_THRESHOLD) ? \
(1U << (DFSDM_FLTAWSR_AWHTF_Pos + channel)) : \
(1U << channel);
#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
hdfsdm_filter->AwdCallback(hdfsdm_filter, channel, threshold);
#else
HAL_DFSDM_FilterAwdCallback(hdfsdm_filter, channel, threshold);
#endif
}else if (((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_AWDF) != 0U) && \ ((hdfsdm_filter->Instance->FLTCR2 & DFSDM_FLTCR2_AWDIE) != 0U)) { ... }
else if((hdfsdm_filter->Instance == DFSDM1_Filter0) && \
((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_CKABF) != 0U) && \
((hdfsdm_filter->Instance->FLTCR2 & DFSDM_FLTCR2_CKABIE) != 0U))
{
uint32_t reg = 0U;
uint32_t channel = 0U;
reg = ((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_CKABF) >> DFSDM_FLTISR_CKABF_Pos);
while(channel < DFSDM1_CHANNEL_NUMBER)
{
if(((reg & 1U) != 0U) && (a_dfsdm1ChannelHandle[channel] != NULL))
{
if((a_dfsdm1ChannelHandle[channel]->Instance->CHCFGR1 & DFSDM_CHCFGR1_CKABEN) != 0U)
{
hdfsdm_filter->Instance->FLTICR = (1U << (DFSDM_FLTICR_CLRCKABF_Pos + channel));
#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
a_dfsdm1ChannelHandle[channel]->CkabCallback(a_dfsdm1ChannelHandle[channel]);
#else
HAL_DFSDM_ChannelCkabCallback(a_dfsdm1ChannelHandle[channel]);
#endif
}if ((a_dfsdm1ChannelHandle[channel]->Instance->CHCFGR1 & DFSDM_CHCFGR1_CKABEN) != 0U) { ... }
}if (((reg & 1U) != 0U) && (a_dfsdm1ChannelHandle[channel] != NULL)) { ... }
channel++;
reg = reg >> 1U;
}while (channel < DFSDM1_CHANNEL_NUMBER) { ... }
}else if ((hdfsdm_filter->Instance == DFSDM1_Filter0) && \ ((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_CKABF) != 0U) && \ ((hdfsdm_filter->Instance->FLTCR2 & DFSDM_FLTCR2_CKABIE) != 0U)) { ... }
#if defined (DFSDM2_Channel0)
else if((hdfsdm_filter->Instance == DFSDM2_Filter0) && \
((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_CKABF) != 0U) && \
((hdfsdm_filter->Instance->FLTCR2 & DFSDM_FLTCR2_CKABIE) != 0U))
{
uint32_t reg = 0U;
uint32_t channel = 0U;
reg = ((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_CKABF) >> DFSDM_FLTISR_CKABF_Pos);
while(channel < DFSDM2_CHANNEL_NUMBER)
{
if(((reg & 1U) != 0U) && (a_dfsdm2ChannelHandle[channel] != NULL))
{
if((a_dfsdm2ChannelHandle[channel]->Instance->CHCFGR1 & DFSDM_CHCFGR1_CKABEN) != 0U)
{
hdfsdm_filter->Instance->FLTICR = (1U << (DFSDM_FLTICR_CLRCKABF_Pos + channel));
#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
a_dfsdm2ChannelHandle[channel]->CkabCallback(a_dfsdm2ChannelHandle[channel]);
#else
HAL_DFSDM_ChannelCkabCallback(a_dfsdm2ChannelHandle[channel]);
#endif
}if ((a_dfsdm2ChannelHandle[channel]->Instance->CHCFGR1 & DFSDM_CHCFGR1_CKABEN) != 0U) { ... }
}if (((reg & 1U) != 0U) && (a_dfsdm2ChannelHandle[channel] != NULL)) { ... }
channel++;
reg = reg >> 1U;
}while (channel < DFSDM2_CHANNEL_NUMBER) { ... }
}else if ((hdfsdm_filter->Instance == DFSDM2_Filter0) && \ ((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_CKABF) != 0U) && \ ((hdfsdm_filter->Instance->FLTCR2 & DFSDM_FLTCR2_CKABIE) != 0U)) { ... }
/* ... */#endif
else if((hdfsdm_filter->Instance == DFSDM1_Filter0) && \
((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_SCDF) != 0U) && \
((hdfsdm_filter->Instance->FLTCR2 & DFSDM_FLTCR2_SCDIE) != 0U))
{
uint32_t reg = 0U;
uint32_t channel = 0U;
reg = ((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_SCDF) >> DFSDM_FLTISR_SCDF_Pos);
while((reg & 1U) == 0U)
{
channel++;
reg = reg >> 1U;
}while ((reg & 1U) == 0U) { ... }
hdfsdm_filter->Instance->FLTICR = (1U << (DFSDM_FLTICR_CLRSCDF_Pos + channel));
#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
a_dfsdm1ChannelHandle[channel]->ScdCallback(a_dfsdm1ChannelHandle[channel]);
#else
HAL_DFSDM_ChannelScdCallback(a_dfsdm1ChannelHandle[channel]);
#endif
}else if ((hdfsdm_filter->Instance == DFSDM1_Filter0) && \ ((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_SCDF) != 0U) && \ ((hdfsdm_filter->Instance->FLTCR2 & DFSDM_FLTCR2_SCDIE) != 0U)) { ... }
#if defined (DFSDM2_Channel0)
else if((hdfsdm_filter->Instance == DFSDM2_Filter0) && \
((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_SCDF) != 0U) && \
((hdfsdm_filter->Instance->FLTCR2 & DFSDM_FLTCR2_SCDIE) != 0U))
{
uint32_t reg = 0U;
uint32_t channel = 0U;
reg = ((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_SCDF) >> DFSDM_FLTISR_SCDF_Pos);
while((reg & 1U) == 0U)
{
channel++;
reg = reg >> 1U;
}while ((reg & 1U) == 0U) { ... }
hdfsdm_filter->Instance->FLTICR = (1U << (DFSDM_FLTICR_CLRSCDF_Pos + channel));
#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
a_dfsdm2ChannelHandle[channel]->ScdCallback(a_dfsdm2ChannelHandle[channel]);
#else
HAL_DFSDM_ChannelScdCallback(a_dfsdm2ChannelHandle[channel]);
#endif
}else if ((hdfsdm_filter->Instance == DFSDM2_Filter0) && \ ((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_SCDF) != 0U) && \ ((hdfsdm_filter->Instance->FLTCR2 & DFSDM_FLTCR2_SCDIE) != 0U)) { ... }
/* ... */#endif
}HAL_DFSDM_IRQHandler (DFSDM_Filter_HandleTypeDef *hdfsdm_filter) { ... }
/* ... */
__weak void HAL_DFSDM_FilterRegConvCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
{
UNUSED(hdfsdm_filter);
/* ... */
}HAL_DFSDM_FilterRegConvCpltCallback (DFSDM_Filter_HandleTypeDef *hdfsdm_filter) { ... }
/* ... */
__weak void HAL_DFSDM_FilterRegConvHalfCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
{
UNUSED(hdfsdm_filter);
/* ... */
}HAL_DFSDM_FilterRegConvHalfCpltCallback (DFSDM_Filter_HandleTypeDef *hdfsdm_filter) { ... }
/* ... */
__weak void HAL_DFSDM_FilterInjConvCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
{
UNUSED(hdfsdm_filter);
/* ... */
}HAL_DFSDM_FilterInjConvCpltCallback (DFSDM_Filter_HandleTypeDef *hdfsdm_filter) { ... }
/* ... */
__weak void HAL_DFSDM_FilterInjConvHalfCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
{
UNUSED(hdfsdm_filter);
/* ... */
}HAL_DFSDM_FilterInjConvHalfCpltCallback (DFSDM_Filter_HandleTypeDef *hdfsdm_filter) { ... }
/* ... */
__weak void HAL_DFSDM_FilterAwdCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
uint32_t Channel, uint32_t Threshold)
{
UNUSED(hdfsdm_filter);
UNUSED(Channel);
UNUSED(Threshold);
/* ... */
}HAL_DFSDM_FilterAwdCallback (DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Channel, uint32_t Threshold) { ... }
/* ... */
__weak void HAL_DFSDM_FilterErrorCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
{
UNUSED(hdfsdm_filter);
/* ... */
}HAL_DFSDM_FilterErrorCallback (DFSDM_Filter_HandleTypeDef *hdfsdm_filter) { ... }
/* ... */
/* ... */
/* ... */
HAL_DFSDM_Filter_StateTypeDef HAL_DFSDM_FilterGetState(const DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
{
return hdfsdm_filter->State;
}HAL_DFSDM_FilterGetState (const DFSDM_Filter_HandleTypeDef *hdfsdm_filter) { ... }
/* ... */
uint32_t HAL_DFSDM_FilterGetError(const DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
{
return hdfsdm_filter->ErrorCode;
}HAL_DFSDM_FilterGetError (const DFSDM_Filter_HandleTypeDef *hdfsdm_filter) { ... }
/* ... */
/* ... */
#if defined(SYSCFG_MCHDLYCR_BSCKSEL)
/* ... */
void HAL_DFSDM_BitstreamClock_Start(void)
{
uint32_t tmp = 0;
tmp = SYSCFG->MCHDLYCR;
tmp = (tmp &(~SYSCFG_MCHDLYCR_BSCKSEL));
SYSCFG->MCHDLYCR = (tmp|SYSCFG_MCHDLYCR_BSCKSEL);
}HAL_DFSDM_BitstreamClock_Start (void) { ... }
/* ... */
void HAL_DFSDM_BitstreamClock_Stop(void)
{
uint32_t tmp = 0U;
tmp = SYSCFG->MCHDLYCR;
tmp = (tmp &(~SYSCFG_MCHDLYCR_BSCKSEL));
SYSCFG->MCHDLYCR = tmp;
}HAL_DFSDM_BitstreamClock_Stop (void) { ... }
/* ... */
void HAL_DFSDM_DisableDelayClock(uint32_t MCHDLY)
{
uint32_t tmp = 0U;
assert_param(IS_DFSDM_DELAY_CLOCK(MCHDLY));
tmp = SYSCFG->MCHDLYCR;
if(MCHDLY == HAL_MCHDLY_CLOCK_DFSDM2)
{
tmp = tmp &(~SYSCFG_MCHDLYCR_MCHDLY2EN);
}if (MCHDLY == HAL_MCHDLY_CLOCK_DFSDM2) { ... }
else
{
tmp = tmp &(~SYSCFG_MCHDLYCR_MCHDLY1EN);
}else { ... }
SYSCFG->MCHDLYCR = tmp;
}HAL_DFSDM_DisableDelayClock (uint32_t MCHDLY) { ... }
/* ... */
void HAL_DFSDM_EnableDelayClock(uint32_t MCHDLY)
{
uint32_t tmp = 0U;
assert_param(IS_DFSDM_DELAY_CLOCK(MCHDLY));
tmp = SYSCFG->MCHDLYCR;
tmp = tmp & ~MCHDLY;
SYSCFG->MCHDLYCR = (tmp|MCHDLY);
}HAL_DFSDM_EnableDelayClock (uint32_t MCHDLY) { ... }
/* ... */
void HAL_DFSDM_ClockIn_SourceSelection(uint32_t source)
{
uint32_t tmp = 0U;
assert_param(IS_DFSDM_CLOCKIN_SELECTION(source));
tmp = SYSCFG->MCHDLYCR;
if((source == HAL_DFSDM2_CKIN_PAD) || (source == HAL_DFSDM2_CKIN_DM))
{
tmp = (tmp & ~SYSCFG_MCHDLYCR_DFSDM2CFG);
if(source == HAL_DFSDM2_CKIN_PAD)
{
source = 0x000000U;
}if (source == HAL_DFSDM2_CKIN_PAD) { ... }
}if ((source == HAL_DFSDM2_CKIN_PAD) || (source == HAL_DFSDM2_CKIN_DM)) { ... }
else
{
tmp = (tmp & ~SYSCFG_MCHDLYCR_DFSDM1CFG);
}else { ... }
SYSCFG->MCHDLYCR = (source|tmp);
}HAL_DFSDM_ClockIn_SourceSelection (uint32_t source) { ... }
/* ... */
void HAL_DFSDM_ClockOut_SourceSelection(uint32_t source)
{
uint32_t tmp = 0U;
assert_param(IS_DFSDM_CLOCKOUT_SELECTION(source));
tmp = SYSCFG->MCHDLYCR;
if((source == HAL_DFSDM2_CKOUT_DFSDM2) || (source == HAL_DFSDM2_CKOUT_M27))
{
tmp = (tmp & ~SYSCFG_MCHDLYCR_DFSDM2CKOSEL);
if(source == HAL_DFSDM2_CKOUT_DFSDM2)
{
source = 0x000U;
}if (source == HAL_DFSDM2_CKOUT_DFSDM2) { ... }
}if ((source == HAL_DFSDM2_CKOUT_DFSDM2) || (source == HAL_DFSDM2_CKOUT_M27)) { ... }
else
{
tmp = (tmp & ~SYSCFG_MCHDLYCR_DFSDM1CKOSEL);
}else { ... }
SYSCFG->MCHDLYCR = (source|tmp);
}HAL_DFSDM_ClockOut_SourceSelection (uint32_t source) { ... }
/* ... */
void HAL_DFSDM_DataIn0_SourceSelection(uint32_t source)
{
uint32_t tmp = 0U;
assert_param(IS_DFSDM_DATAIN0_SRC_SELECTION(source));
tmp = SYSCFG->MCHDLYCR;
if((source == HAL_DATAIN0_DFSDM2_PAD)|| (source == HAL_DATAIN0_DFSDM2_DATAIN1))
{
tmp = (tmp & ~SYSCFG_MCHDLYCR_DFSDM2D0SEL);
if(source == HAL_DATAIN0_DFSDM2_PAD)
{
source = 0x00000U;
}if (source == HAL_DATAIN0_DFSDM2_PAD) { ... }
}if ((source == HAL_DATAIN0_DFSDM2_PAD)|| (source == HAL_DATAIN0_DFSDM2_DATAIN1)) { ... }
else
{
tmp = (tmp & ~SYSCFG_MCHDLYCR_DFSDM1D0SEL);
}else { ... }
SYSCFG->MCHDLYCR = (source|tmp);
}HAL_DFSDM_DataIn0_SourceSelection (uint32_t source) { ... }
/* ... */
void HAL_DFSDM_DataIn2_SourceSelection(uint32_t source)
{
uint32_t tmp = 0U;
assert_param(IS_DFSDM_DATAIN2_SRC_SELECTION(source));
tmp = SYSCFG->MCHDLYCR;
if((source == HAL_DATAIN2_DFSDM2_PAD)|| (source == HAL_DATAIN2_DFSDM2_DATAIN3))
{
tmp = (tmp & ~SYSCFG_MCHDLYCR_DFSDM2D2SEL);
if (source == HAL_DATAIN2_DFSDM2_PAD)
{
source = 0x0000U;
}if (source == HAL_DATAIN2_DFSDM2_PAD) { ... }
}if ((source == HAL_DATAIN2_DFSDM2_PAD)|| (source == HAL_DATAIN2_DFSDM2_DATAIN3)) { ... }
else
{
tmp = (tmp & ~SYSCFG_MCHDLYCR_DFSDM1D2SEL);
}else { ... }
SYSCFG->MCHDLYCR = (source|tmp);
}HAL_DFSDM_DataIn2_SourceSelection (uint32_t source) { ... }
/* ... */
void HAL_DFSDM_DataIn4_SourceSelection(uint32_t source)
{
uint32_t tmp = 0U;
assert_param(IS_DFSDM_DATAIN4_SRC_SELECTION(source));
tmp = SYSCFG->MCHDLYCR;
tmp = (tmp & ~SYSCFG_MCHDLYCR_DFSDM2D4SEL);
SYSCFG->MCHDLYCR = (source|tmp);
}HAL_DFSDM_DataIn4_SourceSelection (uint32_t source) { ... }
/* ... */
void HAL_DFSDM_DataIn6_SourceSelection(uint32_t source)
{
uint32_t tmp = 0U;
assert_param(IS_DFSDM_DATAIN6_SRC_SELECTION(source));
tmp = SYSCFG->MCHDLYCR;
tmp = (tmp & ~SYSCFG_MCHDLYCR_DFSDM2D6SEL);
SYSCFG->MCHDLYCR = (source|tmp);
}HAL_DFSDM_DataIn6_SourceSelection (uint32_t source) { ... }
/* ... */
void HAL_DFSDM_BitStreamClkDistribution_Config(uint32_t source)
{
uint32_t tmp = 0U;
assert_param(IS_DFSDM_BITSTREM_CLK_DISTRIBUTION(source));
tmp = SYSCFG->MCHDLYCR;
if ((source == HAL_DFSDM1_CLKIN0_TIM4OC2) || (source == HAL_DFSDM1_CLKIN2_TIM4OC2))
{
tmp = (tmp & ~SYSCFG_MCHDLYCR_DFSDM1CK02SEL);
}if ((source == HAL_DFSDM1_CLKIN0_TIM4OC2) || (source == HAL_DFSDM1_CLKIN2_TIM4OC2)) { ... }
else if ((source == HAL_DFSDM1_CLKIN1_TIM4OC1) || (source == HAL_DFSDM1_CLKIN3_TIM4OC1))
{
tmp = (tmp & ~SYSCFG_MCHDLYCR_DFSDM1CK13SEL);
}else if ((source == HAL_DFSDM1_CLKIN1_TIM4OC1) || (source == HAL_DFSDM1_CLKIN3_TIM4OC1)) { ... }
else if ((source == HAL_DFSDM2_CLKIN0_TIM3OC4) || (source == HAL_DFSDM2_CLKIN4_TIM3OC4))
{
tmp = (tmp & ~SYSCFG_MCHDLYCR_DFSDM2CK04SEL);
}else if ((source == HAL_DFSDM2_CLKIN0_TIM3OC4) || (source == HAL_DFSDM2_CLKIN4_TIM3OC4)) { ... }
else if ((source == HAL_DFSDM2_CLKIN1_TIM3OC3) || (source == HAL_DFSDM2_CLKIN5_TIM3OC3))
{
tmp = (tmp & ~SYSCFG_MCHDLYCR_DFSDM2CK15SEL);
}else if ((source == HAL_DFSDM2_CLKIN1_TIM3OC3) || (source == HAL_DFSDM2_CLKIN5_TIM3OC3)) { ... }else if ((source == HAL_DFSDM2_CLKIN2_TIM3OC2) || (source == HAL_DFSDM2_CLKIN6_TIM3OC2))
{
tmp = (tmp & ~SYSCFG_MCHDLYCR_DFSDM2CK26SEL);
}else if ((source == HAL_DFSDM2_CLKIN2_TIM3OC2) || (source == HAL_DFSDM2_CLKIN6_TIM3OC2)) { ... }
else
{
tmp = (tmp & ~SYSCFG_MCHDLYCR_DFSDM2CK37SEL);
}else { ... }
if((source == HAL_DFSDM1_CLKIN0_TIM4OC2) ||(source == HAL_DFSDM1_CLKIN1_TIM4OC1)||
(source == HAL_DFSDM2_CLKIN0_TIM3OC4) ||(source == HAL_DFSDM2_CLKIN1_TIM3OC3)||
(source == HAL_DFSDM2_CLKIN2_TIM3OC2) ||(source == HAL_DFSDM2_CLKIN3_TIM3OC1))
{
source = 0x0000U;
}if ((source == HAL_DFSDM1_CLKIN0_TIM4OC2) ||(source == HAL_DFSDM1_CLKIN1_TIM4OC1)|| (source == HAL_DFSDM2_CLKIN0_TIM3OC4) ||(source == HAL_DFSDM2_CLKIN1_TIM3OC3)|| (source == HAL_DFSDM2_CLKIN2_TIM3OC2) ||(source == HAL_DFSDM2_CLKIN3_TIM3OC1)) { ... }
SYSCFG->MCHDLYCR = (source|tmp);
}HAL_DFSDM_BitStreamClkDistribution_Config (uint32_t source) { ... }
/* ... */
void HAL_DFSDM_ConfigMultiChannelDelay(DFSDM_MultiChannelConfigTypeDef* mchdlystruct)
{
uint32_t mchdlyreg = 0U;
assert_param(IS_DFSDM_DFSDM1_CLKOUT(mchdlystruct->DFSDM1ClockOut));
assert_param(IS_DFSDM_DFSDM2_CLKOUT(mchdlystruct->DFSDM2ClockOut));
assert_param(IS_DFSDM_DFSDM1_CLKIN(mchdlystruct->DFSDM1ClockIn));
assert_param(IS_DFSDM_DFSDM2_CLKIN(mchdlystruct->DFSDM2ClockIn));
assert_param(IS_DFSDM_DFSDM1_BIT_CLK((mchdlystruct->DFSDM1BitClkDistribution)));
assert_param(IS_DFSDM_DFSDM2_BIT_CLK(mchdlystruct->DFSDM2BitClkDistribution));
assert_param(IS_DFSDM_DFSDM1_DATA_DISTRIBUTION(mchdlystruct->DFSDM1DataDistribution));
assert_param(IS_DFSDM_DFSDM2_DATA_DISTRIBUTION(mchdlystruct->DFSDM2DataDistribution));
mchdlyreg = (SYSCFG->MCHDLYCR & 0x80103U);
SYSCFG->MCHDLYCR = (mchdlyreg |(mchdlystruct->DFSDM1ClockOut)|(mchdlystruct->DFSDM2ClockOut)|
(mchdlystruct->DFSDM1ClockIn)|(mchdlystruct->DFSDM2ClockIn)|
(mchdlystruct->DFSDM1BitClkDistribution)| (mchdlystruct->DFSDM2BitClkDistribution)|
(mchdlystruct->DFSDM1DataDistribution)| (mchdlystruct->DFSDM2DataDistribution));
}HAL_DFSDM_ConfigMultiChannelDelay (DFSDM_MultiChannelConfigTypeDef* mchdlystruct) { ... }
/* ... */#endif
/* ... */
/* ... */
Exported functions
/* ... */
/* ... */
static void DFSDM_DMARegularHalfConvCplt(DMA_HandleTypeDef *hdma)
{
DFSDM_Filter_HandleTypeDef* hdfsdm_filter = (DFSDM_Filter_HandleTypeDef*) ((DMA_HandleTypeDef*)hdma)->Parent;
#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
hdfsdm_filter->RegConvHalfCpltCallback(hdfsdm_filter);
#else
HAL_DFSDM_FilterRegConvHalfCpltCallback(hdfsdm_filter);
#endif
}DFSDM_DMARegularHalfConvCplt (DMA_HandleTypeDef *hdma) { ... }
/* ... */
static void DFSDM_DMARegularConvCplt(DMA_HandleTypeDef *hdma)
{
DFSDM_Filter_HandleTypeDef* hdfsdm_filter = (DFSDM_Filter_HandleTypeDef*) ((DMA_HandleTypeDef*)hdma)->Parent;
#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
hdfsdm_filter->RegConvCpltCallback(hdfsdm_filter);
#else
HAL_DFSDM_FilterRegConvCpltCallback(hdfsdm_filter);
#endif
}DFSDM_DMARegularConvCplt (DMA_HandleTypeDef *hdma) { ... }
/* ... */
static void DFSDM_DMAInjectedHalfConvCplt(DMA_HandleTypeDef *hdma)
{
DFSDM_Filter_HandleTypeDef* hdfsdm_filter = (DFSDM_Filter_HandleTypeDef*) ((DMA_HandleTypeDef*)hdma)->Parent;
#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
hdfsdm_filter->InjConvHalfCpltCallback(hdfsdm_filter);
#else
HAL_DFSDM_FilterInjConvHalfCpltCallback(hdfsdm_filter);
#endif
}DFSDM_DMAInjectedHalfConvCplt (DMA_HandleTypeDef *hdma) { ... }
/* ... */
static void DFSDM_DMAInjectedConvCplt(DMA_HandleTypeDef *hdma)
{
DFSDM_Filter_HandleTypeDef* hdfsdm_filter = (DFSDM_Filter_HandleTypeDef*) ((DMA_HandleTypeDef*)hdma)->Parent;
#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
hdfsdm_filter->InjConvCpltCallback(hdfsdm_filter);
#else
HAL_DFSDM_FilterInjConvCpltCallback(hdfsdm_filter);
#endif
}DFSDM_DMAInjectedConvCplt (DMA_HandleTypeDef *hdma) { ... }
/* ... */
static void DFSDM_DMAError(DMA_HandleTypeDef *hdma)
{
DFSDM_Filter_HandleTypeDef* hdfsdm_filter = (DFSDM_Filter_HandleTypeDef*) ((DMA_HandleTypeDef*)hdma)->Parent;
hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_DMA;
#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
hdfsdm_filter->ErrorCallback(hdfsdm_filter);
#else
HAL_DFSDM_FilterErrorCallback(hdfsdm_filter);
#endif
}DFSDM_DMAError (DMA_HandleTypeDef *hdma) { ... }
/* ... */
static uint32_t DFSDM_GetInjChannelsNbr(uint32_t Channels)
{
uint32_t nbChannels = 0U;
uint32_t tmp;
tmp = (uint32_t) (Channels & DFSDM_LSB_MASK);
while(tmp != 0U)
{
if((tmp & 1U) != 0U)
{
nbChannels++;
}if ((tmp & 1U) != 0U) { ... }
tmp = (uint32_t) (tmp >> 1U);
}while (tmp != 0U) { ... }
return nbChannels;
}DFSDM_GetInjChannelsNbr (uint32_t Channels) { ... }
/* ... */
static uint32_t DFSDM_GetChannelFromInstance(const DFSDM_Channel_TypeDef *Instance)
{
uint32_t channel;
#if defined(DFSDM2_Channel0)
if((Instance == DFSDM1_Channel0) || (Instance == DFSDM2_Channel0))
{
channel = 0U;
}if ((Instance == DFSDM1_Channel0) || (Instance == DFSDM2_Channel0)) { ... }
else if((Instance == DFSDM1_Channel1) || (Instance == DFSDM2_Channel1))
{
channel = 1U;
}else if ((Instance == DFSDM1_Channel1) || (Instance == DFSDM2_Channel1)) { ... }
else if((Instance == DFSDM1_Channel2) || (Instance == DFSDM2_Channel2))
{
channel = 2U;
}else if ((Instance == DFSDM1_Channel2) || (Instance == DFSDM2_Channel2)) { ... }
else if((Instance == DFSDM1_Channel3) || (Instance == DFSDM2_Channel3))
{
channel = 3U;
}else if ((Instance == DFSDM1_Channel3) || (Instance == DFSDM2_Channel3)) { ... }
else if(Instance == DFSDM2_Channel4)
{
channel = 4U;
}else if (Instance == DFSDM2_Channel4) { ... }
else if(Instance == DFSDM2_Channel5)
{
channel = 5U;
}else if (Instance == DFSDM2_Channel5) { ... }
else if(Instance == DFSDM2_Channel6)
{
channel = 6U;
}else if (Instance == DFSDM2_Channel6) { ... }
else
{
channel = 7U;
}else { ... }
/* ... */
#else
if(Instance == DFSDM1_Channel0)
{
channel = 0U;
}if (Instance == DFSDM1_Channel0) { ... }
else if(Instance == DFSDM1_Channel1)
{
channel = 1U;
}else if (Instance == DFSDM1_Channel1) { ... }
else if(Instance == DFSDM1_Channel2)
{
channel = 2U;
}else if (Instance == DFSDM1_Channel2) { ... }
else
{
channel = 3U;
}else { ... }
/* ... */#endif
return channel;
}DFSDM_GetChannelFromInstance (const DFSDM_Channel_TypeDef *Instance) { ... }
/* ... */
static void DFSDM_RegConvStart(DFSDM_Filter_HandleTypeDef* hdfsdm_filter)
{
if(hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SW_TRIGGER)
{
hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_RSWSTART;
}if (hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SW_TRIGGER) { ... }
else
{
hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_DFEN);
hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_RSYNC;
hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_DFEN;
if(hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_INJ)
{
if(hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SW_TRIGGER)
{
hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_JSWSTART;
}if (hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SW_TRIGGER) { ... }
hdfsdm_filter->InjConvRemaining = (hdfsdm_filter->InjectedScanMode == ENABLE) ? \
hdfsdm_filter->InjectedChannelsNbr : 1U;
}if (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_INJ) { ... }
}else { ... }
hdfsdm_filter->State = (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) ? \
HAL_DFSDM_FILTER_STATE_REG : HAL_DFSDM_FILTER_STATE_REG_INJ;
}DFSDM_RegConvStart (DFSDM_Filter_HandleTypeDef* hdfsdm_filter) { ... }
/* ... */
static void DFSDM_RegConvStop(DFSDM_Filter_HandleTypeDef* hdfsdm_filter)
{
hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_DFEN);
if(hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SYNC_TRIGGER)
{
hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_RSYNC);
}if (hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SYNC_TRIGGER) { ... }
hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_DFEN;
if(hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG_INJ)
{
if(hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SW_TRIGGER)
{
hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_JSWSTART;
}if (hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SW_TRIGGER) { ... }
hdfsdm_filter->InjConvRemaining = (hdfsdm_filter->InjectedScanMode == ENABLE) ? \
hdfsdm_filter->InjectedChannelsNbr : 1U;
}if (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG_INJ) { ... }
hdfsdm_filter->State = (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG) ? \
HAL_DFSDM_FILTER_STATE_READY : HAL_DFSDM_FILTER_STATE_INJ;
}DFSDM_RegConvStop (DFSDM_Filter_HandleTypeDef* hdfsdm_filter) { ... }
/* ... */
static void DFSDM_InjConvStart(DFSDM_Filter_HandleTypeDef* hdfsdm_filter)
{
if(hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SW_TRIGGER)
{
hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_JSWSTART;
}if (hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SW_TRIGGER) { ... }
else
{
hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_DFEN);
if(hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SYNC_TRIGGER)
{
hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_JSYNC;
}if (hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SYNC_TRIGGER) { ... }
else
{
hdfsdm_filter->Instance->FLTCR1 |= hdfsdm_filter->ExtTriggerEdge;
}else { ... }
hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_DFEN;
if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG) && \
(hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SW_TRIGGER))
{
hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_RSWSTART;
}if ((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG) && \ (hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SW_TRIGGER)) { ... }
}else { ... }
hdfsdm_filter->State = (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) ? \
HAL_DFSDM_FILTER_STATE_INJ : HAL_DFSDM_FILTER_STATE_REG_INJ;
}DFSDM_InjConvStart (DFSDM_Filter_HandleTypeDef* hdfsdm_filter) { ... }
/* ... */
static void DFSDM_InjConvStop(DFSDM_Filter_HandleTypeDef* hdfsdm_filter)
{
hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_DFEN);
if(hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SYNC_TRIGGER)
{
hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_JSYNC);
}if (hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SYNC_TRIGGER) { ... }
else if(hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_EXT_TRIGGER)
{
hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_JEXTEN);
}else if (hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_EXT_TRIGGER) { ... }
else
{
}else { ... }
hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_DFEN;
if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG_INJ) && \
(hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SW_TRIGGER))
{
hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_RSWSTART;
}if ((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG_INJ) && \ (hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SW_TRIGGER)) { ... }
hdfsdm_filter->InjConvRemaining = (hdfsdm_filter->InjectedScanMode == ENABLE) ? \
hdfsdm_filter->InjectedChannelsNbr : 1U;
hdfsdm_filter->State = (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_INJ) ? \
HAL_DFSDM_FILTER_STATE_READY : HAL_DFSDM_FILTER_STATE_REG;
}DFSDM_InjConvStop (DFSDM_Filter_HandleTypeDef* hdfsdm_filter) { ... }
/* ... */
Private functions
/* ... */
/* ... */#endif /* ... */
#endif
/* ... */