mfxstm32l152 + 0/2 examples
CodeScope will show references to MFX_IO_Write() from the following samples and libraries:
 
Symbols
loading...
Files
loading...
CodeScopeSTM32 Libraries and Samplesmfxstm32l152MFX_IO_Write()

MFX_IO_Write() function

Syntax

void MFX_IO_Write(uint16_t addr,     uint8_t reg,     uint8_t value);

Arguments

addr

reg

value

Examples

MFX_IO_Write() is referenced by 2 libraries and example projects.

References

LocationReferrerText
mfxstm32l152.h:610
void MFX_IO_Write(uint16_t addr, uint8_t reg, uint8_t value);
mfxstm32l152.c:205mfxstm32l152_Reset()
MFX_IO_Write(DeviceAddr, MFXSTM32L152_REG_ADR_SYS_CTRL, MFXSTM32L152_SWRST);
mfxstm32l152.c:219mfxstm32l152_LowPower()
MFX_IO_Write(DeviceAddr, MFXSTM32L152_REG_ADR_SYS_CTRL, MFXSTM32L152_STANDBY);
mfxstm32l152.c:309mfxstm32l152_EnableITSource()
MFX_IO_Write(DeviceAddr, MFXSTM32L152_REG_ADR_IRQ_SRC_EN, tmp);
mfxstm32l152.c:337mfxstm32l152_DisableITSource()
MFX_IO_Write(DeviceAddr, MFXSTM32L152_REG_ADR_IRQ_SRC_EN, tmp);
mfxstm32l152.c:380mfxstm32l152_ClearGlobalIT()
MFX_IO_Write(DeviceAddr, MFXSTM32L152_REG_ADR_IRQ_ACK, Source);
mfxstm32l152.c:405mfxstm32l152_SetIrqOutPinPolarity()
MFX_IO_Write(DeviceAddr, MFXSTM32L152_REG_ADR_MFX_IRQ_OUT, tmp);
mfxstm32l152.c:434mfxstm32l152_SetIrqOutPinType()
MFX_IO_Write(DeviceAddr, MFXSTM32L152_REG_ADR_MFX_IRQ_OUT, tmp);
mfxstm32l152.c:481mfxstm32l152_IO_Start()
MFX_IO_Write(DeviceAddr, MFXSTM32L152_REG_ADR_SYS_CTRL, mode);
mfxstm32l152.c:918mfxstm32l152_IO_ClearIT()
MFX_IO_Write(DeviceAddr, MFXSTM32L152_REG_ADR_IRQ_GPI_ACK1, pin_0_7);
mfxstm32l152.c:922mfxstm32l152_IO_ClearIT()
MFX_IO_Write(DeviceAddr, MFXSTM32L152_REG_ADR_IRQ_GPI_ACK2, pin_8_15);
mfxstm32l152.c:926mfxstm32l152_IO_ClearIT()
MFX_IO_Write(DeviceAddr, MFXSTM32L152_REG_ADR_IRQ_GPI_ACK3, pin_16_23);
mfxstm32l152.c:954mfxstm32l152_IO_EnableAF()
MFX_IO_Write(DeviceAddr, MFXSTM32L152_REG_ADR_SYS_CTRL, mode);
mfxstm32l152.c:980mfxstm32l152_IO_DisableAF()
MFX_IO_Write(DeviceAddr, MFXSTM32L152_REG_ADR_SYS_CTRL, mode);
mfxstm32l152.c:1005mfxstm32l152_TS_Start()
MFX_IO_Write(DeviceAddr, MFXSTM32L152_REG_ADR_SYS_CTRL, mode);
mfxstm32l152.c:1016mfxstm32l152_TS_Start()
MFX_IO_Write(DeviceAddr, MFXSTM32L152_TS_SETTLING, 0x32);
mfxstm32l152.c:1017mfxstm32l152_TS_Start()
MFX_IO_Write(DeviceAddr, MFXSTM32L152_TS_TOUCH_DET_DELAY, 0x5);
mfxstm32l152.c:1018mfxstm32l152_TS_Start()
MFX_IO_Write(DeviceAddr, MFXSTM32L152_TS_AVE, 0x04);
mfxstm32l152.c:1021mfxstm32l152_TS_Start()
MFX_IO_Write(DeviceAddr, MFXSTM32L152_TS_FIFO_TH, 0x01);
mfxstm32l152.c:1024mfxstm32l152_TS_Start()
MFX_IO_Write(DeviceAddr, MFXSTM32L152_TS_FIFO_TH, MFXSTM32L152_TS_CLEAR_FIFO);
mfxstm32l152.c:1029mfxstm32l152_TS_Start()
MFX_IO_Write(DeviceAddr, MFXSTM32L152_TS_TRACK, 0x00);
mfxstm32l152.c:1081mfxstm32l152_TS_GetXY()
MFX_IO_Write(DeviceAddr, MFXSTM32L152_TS_FIFO_TH, MFXSTM32L152_TS_CLEAR_FIFO);
mfxstm32l152.c:1150mfxstm32l152_IDD_Start()
MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_CTRL, mode);
mfxstm32l152.c:1173mfxstm32l152_IDD_Config()
MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_SYS_CTRL, mode);
mfxstm32l152.c:1180mfxstm32l152_IDD_Config()
MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_CTRL, value);
mfxstm32l152.c:1185mfxstm32l152_IDD_Config()
MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_PRE_DELAY, value);
mfxstm32l152.c:1189mfxstm32l152_IDD_Config()
MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_SHUNT0_MSB, value);
mfxstm32l152.c:1191mfxstm32l152_IDD_Config()
MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_SHUNT0_LSB, value);
mfxstm32l152.c:1195mfxstm32l152_IDD_Config()
MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_SHUNT1_MSB, value);
mfxstm32l152.c:1197mfxstm32l152_IDD_Config()
MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_SHUNT1_LSB, value);
mfxstm32l152.c:1201mfxstm32l152_IDD_Config()
MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_SHUNT2_MSB, value);
mfxstm32l152.c:1203mfxstm32l152_IDD_Config()
MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_SHUNT2_LSB, value);
mfxstm32l152.c:1207mfxstm32l152_IDD_Config()
MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_SHUNT3_MSB, value);
mfxstm32l152.c:1209mfxstm32l152_IDD_Config()
MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_SHUNT3_LSB, value);
mfxstm32l152.c:1213mfxstm32l152_IDD_Config()
MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_SHUNT4_MSB, value);
mfxstm32l152.c:1215mfxstm32l152_IDD_Config()
MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_SHUNT4_LSB, value);
mfxstm32l152.c:1219mfxstm32l152_IDD_Config()
MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_SH0_STABILIZATION, value);
mfxstm32l152.c:1223mfxstm32l152_IDD_Config()
MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_SH1_STABILIZATION, value);
mfxstm32l152.c:1227mfxstm32l152_IDD_Config()
MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_SH2_STABILIZATION, value);
mfxstm32l152.c:1231mfxstm32l152_IDD_Config()
MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_SH3_STABILIZATION, value);
mfxstm32l152.c:1235mfxstm32l152_IDD_Config()
MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_SH4_STABILIZATION, value);
mfxstm32l152.c:1239mfxstm32l152_IDD_Config()
MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_GAIN_MSB, value);
mfxstm32l152.c:1241mfxstm32l152_IDD_Config()
MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_GAIN_LSB, value);
mfxstm32l152.c:1245mfxstm32l152_IDD_Config()
MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_VDD_MIN_MSB, value);
mfxstm32l152.c:1247mfxstm32l152_IDD_Config()
MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_VDD_MIN_LSB, value);
mfxstm32l152.c:1251mfxstm32l152_IDD_Config()
MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_NBR_OF_MEAS, value);
mfxstm32l152.c:1256mfxstm32l152_IDD_Config()
MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_MEAS_DELTA_DELAY, value);
mfxstm32l152.c:1260mfxstm32l152_IDD_Config()
MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_SHUNTS_ON_BOARD, value);
mfxstm32l152.c:1282mfxstm32l152_IDD_ConfigShuntNbLimit()
MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_CTRL, mode);
mfxstm32l152.c:1444mfxstm32l152_WriteReg()
MFX_IO_Write((uint8_t) DeviceAddr, RegAddr, Value);
mfxstm32l152.c:1527mfxstm32l152_reg24_setPinValue()
MFX_IO_Write(DeviceAddr, RegisterAddr, tmp);
mfxstm32l152.c:1546mfxstm32l152_reg24_setPinValue()
MFX_IO_Write(DeviceAddr, RegisterAddr+1, tmp);
mfxstm32l152.c:1565mfxstm32l152_reg24_setPinValue()
MFX_IO_Write(DeviceAddr, RegisterAddr+2, tmp);

Call Tree