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/**
******************************************************************************
* @file stm324xg_eval_sram.c
* @author MCD Application Team
* @brief This file includes the SRAM driver for the IS61WV102416BLL-10MLI memory
* device mounted on STM324xG-EVAL evaluation board.
******************************************************************************
* @attention
*
* Copyright (c) 2017 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* File Info : -----------------------------------------------------------------
User NOTES
1. How To use this driver:
--------------------------
- This driver is used to drive the IS61WV102416BLL-10MLI SRAM external memory mounted
on STM324xG-EVAL evaluation board.
- This driver does not need a specific component driver for the SRAM device
to be included with.
2. Driver description:
---------------------
+ Initialization steps:
o Initialize the SRAM external memory using the BSP_SRAM_Init() function. This
function includes the MSP layer hardware resources initialization and the
FMC controller configuration to interface with the external SRAM memory.
+ SRAM read/write operations
o SRAM external memory can be accessed with read/write operations once it is
initialized.
Read/write operation can be performed with AHB access using the functions
BSP_SRAM_ReadData()/BSP_SRAM_WriteData(), or by DMA transfer using the functions
BSP_SRAM_ReadData_DMA()/BSP_SRAM_WriteData_DMA().
o The AHB access is performed with 16-bit width transaction, the DMA transfer
configuration is fixed at single (no burst) halfword transfer
(see the SRAM_MspInit() static function).
o User can implement his own functions for read/write access with his desired
configurations.
o If interrupt mode is used for DMA transfer, the function BSP_SRAM_DMA_IRQHandler()
is called in IRQ handler file, to serve the generated interrupt once the DMA
transfer is complete.
------------------------------------------------------------------------------*/
/* Includes ------------------------------------------------------------------*/
#include "stm324xg_eval_sram.h"
/** @addtogroup BSP
* @{
*/
/** @addtogroup STM324xG_EVAL
* @{
*/
/** @defgroup STM324xG_EVAL_SRAM STM324xG EVAL SRAM
* @{
*/
/** @defgroup STM324xG_EVAL_SRAM_Private_Variables STM324xG EVAL SRAM Private Variables
* @{
*/
static SRAM_HandleTypeDef sramHandle;
static FMC_NORSRAM_TimingTypeDef Timing;
/**
* @}
*/
/** @defgroup STM324xG_EVAL_SRAM_Private_Functions STM324xG EVAL SRAM Private Functions
* @{
*/
/**
* @brief Initializes the SRAM device.
* @retval SRAM status
*/
uint8_t BSP_SRAM_Init(void)
{
sramHandle.Instance = FMC_NORSRAM_DEVICE;
sramHandle.Extended = FMC_NORSRAM_EXTENDED_DEVICE;
/* SRAM device configuration */
Timing.AddressSetupTime = 2;
Timing.AddressHoldTime = 1;
Timing.DataSetupTime = 2;
Timing.BusTurnAroundDuration = 1;
Timing.CLKDivision = 2;
Timing.DataLatency = 2;
Timing.AccessMode = FSMC_ACCESS_MODE_A;
sramHandle.Init.NSBank = FSMC_NORSRAM_BANK2;
sramHandle.Init.DataAddressMux = FSMC_DATA_ADDRESS_MUX_DISABLE;
sramHandle.Init.MemoryType = FSMC_MEMORY_TYPE_SRAM;
sramHandle.Init.MemoryDataWidth = SRAM_MEMORY_WIDTH;
sramHandle.Init.BurstAccessMode = SRAM_BURSTACCESS;
sramHandle.Init.WaitSignalPolarity = FSMC_WAIT_SIGNAL_POLARITY_LOW;
sramHandle.Init.WrapMode = FSMC_WRAP_MODE_DISABLE;
sramHandle.Init.WaitSignalActive = FSMC_WAIT_TIMING_BEFORE_WS;
sramHandle.Init.WriteOperation = FSMC_WRITE_OPERATION_ENABLE;
sramHandle.Init.WaitSignal = FSMC_WAIT_SIGNAL_DISABLE;
sramHandle.Init.ExtendedMode = FSMC_EXTENDED_MODE_DISABLE;
sramHandle.Init.AsynchronousWait = FSMC_ASYNCHRONOUS_WAIT_DISABLE;
sramHandle.Init.WriteBurst = SRAM_WRITEBURST;
/* SRAM controller initialization */
BSP_SRAM_MspInit();
if(HAL_SRAM_Init(&sramHandle, &Timing, &Timing) != HAL_OK)
{
return SRAM_ERROR;
}
else
{
return SRAM_OK;
}
}
/**
* @brief Reads an amount of data from the SRAM device in polling mode.
* @param uwStartAddress : Read start address
* @param pData: Pointer to data to be read
* @param uwDataSize: Size of read data from the memory
* @retval SRAM status
*/
uint8_t BSP_SRAM_ReadData(uint32_t uwStartAddress, uint16_t *pData, uint32_t uwDataSize)
{
if(HAL_SRAM_Read_16b(&sramHandle, (uint32_t *)uwStartAddress, pData, uwDataSize) != HAL_OK)
{
return SRAM_ERROR;
}
else
{
return SRAM_OK;
}
}
/**
* @brief Reads an amount of data from the SRAM device in DMA mode.
* @param uwStartAddress : Read start address
* @param pData: Pointer to data to be read
* @param uwDataSize: Size of read data from the memory
* @retval SRAM status
*/
uint8_t BSP_SRAM_ReadData_DMA(uint32_t uwStartAddress, uint16_t *pData, uint32_t uwDataSize)
{
if(HAL_SRAM_Read_DMA(&sramHandle, (uint32_t *)uwStartAddress, (uint32_t *)pData, uwDataSize) != HAL_OK)
{
return SRAM_ERROR;
}
else
{
return SRAM_OK;
}
}
/**
* @brief Writes an amount of data from the SRAM device in polling mode.
* @param uwStartAddress: Write start address
* @param pData: Pointer to data to be written
* @param uwDataSize: Size of written data from the memory
* @retval SRAM status
*/
uint8_t BSP_SRAM_WriteData(uint32_t uwStartAddress, uint16_t *pData, uint32_t uwDataSize)
{
if(HAL_SRAM_Write_16b(&sramHandle, (uint32_t *)uwStartAddress, pData, uwDataSize) != HAL_OK)
{
return SRAM_ERROR;
}
else
{
return SRAM_OK;
}
}
/**
* @brief Writes an amount of data from the SRAM device in DMA mode.
* @param uwStartAddress: Write start address
* @param pData: Pointer to data to be written
* @param uwDataSize: Size of written data from the memory
* @retval SRAM status
*/
uint8_t BSP_SRAM_WriteData_DMA(uint32_t uwStartAddress, uint16_t *pData, uint32_t uwDataSize)
{
if(HAL_SRAM_Write_DMA(&sramHandle, (uint32_t *)uwStartAddress, (uint32_t *)pData, uwDataSize) != HAL_OK)
{
return SRAM_ERROR;
}
else
{
return SRAM_OK;
}
}
/**
* @brief Handles SRAM DMA transfer interrupt request.
*/
void BSP_SRAM_DMA_IRQHandler(void)
{
HAL_DMA_IRQHandler(sramHandle.hdma);
}
/**
* @brief Initializes SRAM MSP.
*/
__weak void BSP_SRAM_MspInit(void)
{
static DMA_HandleTypeDef dmaHandle;
GPIO_InitTypeDef GPIO_Init_Structure;
SRAM_HandleTypeDef *hsram = &sramHandle;
/* Enable FMC clock */
__HAL_RCC_FSMC_CLK_ENABLE();
/* Enable chosen DMAx clock */
__SRAM_DMAx_CLK_ENABLE();
/* Enable GPIOs clock */
__HAL_RCC_GPIOD_CLK_ENABLE();
__HAL_RCC_GPIOE_CLK_ENABLE();
__HAL_RCC_GPIOF_CLK_ENABLE();
__HAL_RCC_GPIOG_CLK_ENABLE();
/* Common GPIO configuration */
GPIO_Init_Structure.Mode = GPIO_MODE_AF_PP;
GPIO_Init_Structure.Pull = GPIO_PULLUP;
GPIO_Init_Structure.Speed = GPIO_SPEED_HIGH;
GPIO_Init_Structure.Alternate = GPIO_AF12_FSMC;
/* GPIOD configuration */
GPIO_Init_Structure.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_4 | GPIO_PIN_5 | GPIO_PIN_8 |\
GPIO_PIN_9 | GPIO_PIN_10 | GPIO_PIN_11 | GPIO_PIN_12 | GPIO_PIN_13 |\
GPIO_PIN_14 | GPIO_PIN_15;
HAL_GPIO_Init(GPIOD, &GPIO_Init_Structure);
/* GPIOE configuration */
GPIO_Init_Structure.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_3| GPIO_PIN_4 | GPIO_PIN_7 |\
GPIO_PIN_8 | GPIO_PIN_9 | GPIO_PIN_10 | GPIO_PIN_11 | GPIO_PIN_12 |\
GPIO_PIN_13 | GPIO_PIN_14 | GPIO_PIN_15;
HAL_GPIO_Init(GPIOE, &GPIO_Init_Structure);
/* GPIOF configuration */
GPIO_Init_Structure.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2| GPIO_PIN_3 | GPIO_PIN_4 |\
GPIO_PIN_5 | GPIO_PIN_12 | GPIO_PIN_13 | GPIO_PIN_14 | GPIO_PIN_15;
HAL_GPIO_Init(GPIOF, &GPIO_Init_Structure);
/* GPIOG configuration */
GPIO_Init_Structure.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2| GPIO_PIN_3 | GPIO_PIN_4 |\
GPIO_PIN_5 | GPIO_PIN_9;
HAL_GPIO_Init(GPIOG, &GPIO_Init_Structure);
/* Configure common DMA parameters */
dmaHandle.Init.Channel = SRAM_DMAx_CHANNEL;
dmaHandle.Init.Direction = DMA_MEMORY_TO_MEMORY;
dmaHandle.Init.PeriphInc = DMA_PINC_ENABLE;
dmaHandle.Init.MemInc = DMA_MINC_ENABLE;
dmaHandle.Init.PeriphDataAlignment = DMA_PDATAALIGN_HALFWORD;
dmaHandle.Init.MemDataAlignment = DMA_MDATAALIGN_HALFWORD;
dmaHandle.Init.Mode = DMA_NORMAL;
dmaHandle.Init.Priority = DMA_PRIORITY_HIGH;
dmaHandle.Init.FIFOMode = DMA_FIFOMODE_DISABLE;
dmaHandle.Init.FIFOThreshold = DMA_FIFO_THRESHOLD_FULL;
dmaHandle.Init.MemBurst = DMA_MBURST_INC8;
dmaHandle.Init.PeriphBurst = DMA_PBURST_INC8;
dmaHandle.Instance = SRAM_DMAx_STREAM;
/* Associate the DMA handle */
__HAL_LINKDMA(hsram, hdma, dmaHandle);
/* Deinitialize the stream for new transfer */
HAL_DMA_DeInit(&dmaHandle);
/* Configure the DMA stream */
HAL_DMA_Init(&dmaHandle);
/* NVIC configuration for DMA transfer complete interrupt */
HAL_NVIC_SetPriority(SRAM_DMAx_IRQn, 0x0F, 0);
HAL_NVIC_EnableIRQ(SRAM_DMAx_IRQn);
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/