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/* ... */
/* ... */
#include "stm32469i_eval_sram.h"
/* ... */
/* ... */
/* ... */
/* ... */
/* ... */
/* ... */
/* ... */
/* ... */
/* ... */
/* ... */
static SRAM_HandleTypeDef sramHandle;
static FMC_NORSRAM_TimingTypeDef Timing;
/* ... */
/* ... */
/* ... */
/* ... */
/* ... */
/* ... */
/* ... */
uint8_t BSP_SRAM_Init(void)
{
sramHandle.Instance = FMC_NORSRAM_DEVICE;
sramHandle.Extended = FMC_NORSRAM_EXTENDED_DEVICE;
Timing.AddressSetupTime = 2;
Timing.AddressHoldTime = 1;
Timing.DataSetupTime = 2;
Timing.BusTurnAroundDuration = 1;
Timing.CLKDivision = 2;
Timing.DataLatency = 2;
Timing.AccessMode = FMC_ACCESS_MODE_A;
sramHandle.Init.NSBank = FMC_NORSRAM_BANK2;
sramHandle.Init.DataAddressMux = FMC_DATA_ADDRESS_MUX_DISABLE;
sramHandle.Init.MemoryType = FMC_MEMORY_TYPE_SRAM;
sramHandle.Init.MemoryDataWidth = SRAM_MEMORY_WIDTH;
sramHandle.Init.BurstAccessMode = SRAM_BURSTACCESS;
sramHandle.Init.WaitSignalPolarity = FMC_WAIT_SIGNAL_POLARITY_LOW;
sramHandle.Init.WrapMode = FMC_WRAP_MODE_DISABLE;
sramHandle.Init.WaitSignalActive = FMC_WAIT_TIMING_BEFORE_WS;
sramHandle.Init.WriteOperation = FMC_WRITE_OPERATION_ENABLE;
sramHandle.Init.WaitSignal = FMC_WAIT_SIGNAL_DISABLE;
sramHandle.Init.ExtendedMode = FMC_EXTENDED_MODE_DISABLE;
sramHandle.Init.AsynchronousWait = FMC_ASYNCHRONOUS_WAIT_DISABLE;
sramHandle.Init.WriteBurst = SRAM_WRITEBURST;
sramHandle.Init.ContinuousClock = CONTINUOUSCLOCK_FEATURE;
BSP_SRAM_MspInit(&sramHandle, (void*)NULL);
if(HAL_SRAM_Init(&sramHandle, &Timing, &Timing) != HAL_OK)
{
return SRAM_ERROR;
}if (HAL_SRAM_Init(&sramHandle, &Timing, &Timing) != HAL_OK) { ... }
else
{
return SRAM_OK;
}else { ... }
}{ ... }
/* ... */
uint8_t BSP_SRAM_DeInit(void)
{
static uint8_t sramstatus = SRAM_ERROR;
sramHandle.Instance = FMC_NORSRAM_DEVICE;
if(HAL_SRAM_DeInit(&sramHandle) == HAL_OK)
{
sramstatus = SRAM_OK;
BSP_SRAM_MspDeInit(&sramHandle, (void *)NULL);
}if (HAL_SRAM_DeInit(&sramHandle) == HAL_OK) { ... }
return sramstatus;
}{ ... }
/* ... */
uint8_t BSP_SRAM_ReadData(uint32_t uwStartAddress, uint16_t *pData, uint32_t uwDataSize)
{
if(HAL_SRAM_Read_16b(&sramHandle, (uint32_t *)uwStartAddress, pData, uwDataSize) != HAL_OK)
{
return SRAM_ERROR;
}if (HAL_SRAM_Read_16b(&sramHandle, (uint32_t *)uwStartAddress, pData, uwDataSize) != HAL_OK) { ... }
else
{
return SRAM_OK;
}else { ... }
}{ ... }
/* ... */
uint8_t BSP_SRAM_ReadData_DMA(uint32_t uwStartAddress, uint16_t *pData, uint32_t uwDataSize)
{
if(HAL_SRAM_Read_DMA(&sramHandle, (uint32_t *)uwStartAddress, (uint32_t *)pData, uwDataSize) != HAL_OK)
{
return SRAM_ERROR;
}if (HAL_SRAM_Read_DMA(&sramHandle, (uint32_t *)uwStartAddress, (uint32_t *)pData, uwDataSize) != HAL_OK) { ... }
else
{
return SRAM_OK;
}else { ... }
}{ ... }
/* ... */
uint8_t BSP_SRAM_WriteData(uint32_t uwStartAddress, uint16_t *pData, uint32_t uwDataSize)
{
if(HAL_SRAM_Write_16b(&sramHandle, (uint32_t *)uwStartAddress, pData, uwDataSize) != HAL_OK)
{
return SRAM_ERROR;
}if (HAL_SRAM_Write_16b(&sramHandle, (uint32_t *)uwStartAddress, pData, uwDataSize) != HAL_OK) { ... }
else
{
return SRAM_OK;
}else { ... }
}{ ... }
/* ... */
uint8_t BSP_SRAM_WriteData_DMA(uint32_t uwStartAddress, uint16_t *pData, uint32_t uwDataSize)
{
if(HAL_SRAM_Write_DMA(&sramHandle, (uint32_t *)uwStartAddress, (uint32_t *)pData, uwDataSize) != HAL_OK)
{
return SRAM_ERROR;
}if (HAL_SRAM_Write_DMA(&sramHandle, (uint32_t *)uwStartAddress, (uint32_t *)pData, uwDataSize) != HAL_OK) { ... }
else
{
return SRAM_OK;
}else { ... }
}{ ... }
/* ... */
void BSP_SRAM_DMA_IRQHandler(void)
{
HAL_DMA_IRQHandler(sramHandle.hdma);
}{ ... }
/* ... */
__weak void BSP_SRAM_MspInit(SRAM_HandleTypeDef *hsram, void *Params)
{
static DMA_HandleTypeDef dma_handle;
GPIO_InitTypeDef gpio_init_structure;
if(hsram != (SRAM_HandleTypeDef *)NULL)
{
__HAL_RCC_FMC_CLK_ENABLE();
__SRAM_DMAx_CLK_ENABLE();
__HAL_RCC_GPIOD_CLK_ENABLE();
__HAL_RCC_GPIOE_CLK_ENABLE();
__HAL_RCC_GPIOF_CLK_ENABLE();
__HAL_RCC_GPIOG_CLK_ENABLE();
gpio_init_structure.Mode = GPIO_MODE_AF_PP;
gpio_init_structure.Pull = GPIO_PULLUP;
gpio_init_structure.Speed = GPIO_SPEED_HIGH;
gpio_init_structure.Alternate = GPIO_AF12_FMC;
gpio_init_structure.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_3 | GPIO_PIN_4 | GPIO_PIN_5 | GPIO_PIN_8 |\
GPIO_PIN_9 | GPIO_PIN_10 | GPIO_PIN_11 | GPIO_PIN_12 | GPIO_PIN_13 |\
GPIO_PIN_14 | GPIO_PIN_15;
HAL_GPIO_Init(GPIOD, &gpio_init_structure);
gpio_init_structure.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_3| GPIO_PIN_4 | GPIO_PIN_7 |\
GPIO_PIN_8 | GPIO_PIN_9 | GPIO_PIN_10 | GPIO_PIN_11 | GPIO_PIN_12 |\
GPIO_PIN_13 | GPIO_PIN_14 | GPIO_PIN_15;
HAL_GPIO_Init(GPIOE, &gpio_init_structure);
gpio_init_structure.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2| GPIO_PIN_3 | GPIO_PIN_4 |\
GPIO_PIN_5 | GPIO_PIN_12 | GPIO_PIN_13 | GPIO_PIN_14 | GPIO_PIN_15;
HAL_GPIO_Init(GPIOF, &gpio_init_structure);
gpio_init_structure.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2| GPIO_PIN_3 | GPIO_PIN_4 |\
GPIO_PIN_5 | GPIO_PIN_9;
HAL_GPIO_Init(GPIOG, &gpio_init_structure);
dma_handle.Init.Channel = SRAM_DMAx_CHANNEL;
dma_handle.Init.Direction = DMA_MEMORY_TO_MEMORY;
dma_handle.Init.PeriphInc = DMA_PINC_ENABLE;
dma_handle.Init.MemInc = DMA_MINC_ENABLE;
dma_handle.Init.PeriphDataAlignment = DMA_PDATAALIGN_HALFWORD;
dma_handle.Init.MemDataAlignment = DMA_MDATAALIGN_HALFWORD;
dma_handle.Init.Mode = DMA_NORMAL;
dma_handle.Init.Priority = DMA_PRIORITY_HIGH;
dma_handle.Init.FIFOMode = DMA_FIFOMODE_DISABLE;
dma_handle.Init.FIFOThreshold = DMA_FIFO_THRESHOLD_FULL;
dma_handle.Init.MemBurst = DMA_MBURST_SINGLE;
dma_handle.Init.PeriphBurst = DMA_PBURST_SINGLE;
dma_handle.Instance = SRAM_DMAx_STREAM;
__HAL_LINKDMA(hsram, hdma, dma_handle);
HAL_DMA_DeInit(&dma_handle);
HAL_DMA_Init(&dma_handle);
HAL_NVIC_SetPriority(SRAM_DMAx_IRQn, 5, 0);
HAL_NVIC_EnableIRQ(SRAM_DMAx_IRQn);
}if (hsram != (SRAM_HandleTypeDef *)NULL) { ... }
}{ ... }
/* ... */
__weak void BSP_SRAM_MspDeInit(SRAM_HandleTypeDef *hsram, void *Params)
{
static DMA_HandleTypeDef dma_handle;
if(hsram != (SRAM_HandleTypeDef *)NULL)
{
HAL_NVIC_DisableIRQ(SRAM_DMAx_IRQn);
dma_handle.Instance = SRAM_DMAx_STREAM;
HAL_DMA_DeInit(&dma_handle);
/* ... */
/* ... */
}if (hsram != (SRAM_HandleTypeDef *)NULL) { ... }
}{ ... }
/* ... */
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/* ... */