CMSIS
__IOM is only used within CMSIS.
 
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CodeScopeSTM32 Libraries and SamplesCMSIS__IOM

__IOM macro

Syntax

#define __IOM volatile

References

LocationText
core_cm4.h:232
#define __IOM volatile /*! Defines 'read / write' structure member permissions */
core_cm4.h:413
__IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
core_cm4.h:415
__IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
core_cm4.h:417
__IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
core_cm4.h:419
__IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
core_cm4.h:421
__IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
core_cm4.h:423
__IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
core_cm4.h:448
__IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
core_cm4.h:449
__IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
core_cm4.h:450
__IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
core_cm4.h:451
__IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
core_cm4.h:452
__IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
core_cm4.h:453
__IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
core_cm4.h:454
__IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
core_cm4.h:455
__IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
core_cm4.h:456
__IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
core_cm4.h:457
__IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
core_cm4.h:458
__IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
core_cm4.h:459
__IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
core_cm4.h:460
__IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
core_cm4.h:467
__IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
core_cm4.h:728
__IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
core_cm4.h:766
__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
core_cm4.h:767
__IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
core_cm4.h:768
__IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
core_cm4.h:825
__IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
core_cm4.h:827
__IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
core_cm4.h:829
__IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
core_cm4.h:906
__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
core_cm4.h:907
__IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
core_cm4.h:908
__IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
core_cm4.h:909
__IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
core_cm4.h:910
__IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
core_cm4.h:911
__IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
core_cm4.h:912
__IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
core_cm4.h:914
__IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
core_cm4.h:915
__IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
core_cm4.h:916
__IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
core_cm4.h:918
__IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
core_cm4.h:919
__IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
core_cm4.h:920
__IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
core_cm4.h:922
__IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
core_cm4.h:923
__IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
core_cm4.h:924
__IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
core_cm4.h:926
__IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
core_cm4.h:927
__IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
core_cm4.h:928
__IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
core_cm4.h:1054
__IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
core_cm4.h:1056
__IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
core_cm4.h:1058
__IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
core_cm4.h:1061
__IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
core_cm4.h:1070
__IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
core_cm4.h:1072
__IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
core_cm4.h:1073
__IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
core_cm4.h:1216
__IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
core_cm4.h:1217
__IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
core_cm4.h:1218
__IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
core_cm4.h:1219
__IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
core_cm4.h:1220
__IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
core_cm4.h:1221
__IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
core_cm4.h:1222
__IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
core_cm4.h:1223
__IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
core_cm4.h:1224
__IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
core_cm4.h:1225
__IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
core_cm4.h:1312
__IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */
core_cm4.h:1313
__IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */
core_cm4.h:1314
__IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */
core_cm4.h:1423
__IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
core_cm4.h:1425
__IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
core_cm4.h:1426
__IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */