__ASM - syntax, references, description

References

Location	Text
cmsis_gcc.h:41	#define __ASM __asm
cmsis_gcc.h:40	#ifndef __ASM
cmsis_gcc.h:117	#define __COMPILER_BARRIER() __ASM volatile("":::"memory")
cmsis_gcc.h:228	#define __NOP() __ASM volatile ("nop")
cmsis_gcc.h:234	#define __WFI() __ASM volatile ("wfi":::"memory")
cmsis_gcc.h:242	#define __WFE() __ASM volatile ("wfe":::"memory")
cmsis_gcc.h:249	#define __SEV() __ASM volatile ("sev")
cmsis_gcc.h:260	__ASM volatile ("isb 0xF":::"memory");
cmsis_gcc.h:271	__ASM volatile ("dsb 0xF":::"memory");
cmsis_gcc.h:282	__ASM volatile ("dmb 0xF":::"memory");
cmsis_gcc.h:315	__ASM ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
cmsis_gcc.h:380	__ASM ("rbit %0, %1" : "=r" (result) : "r" (value) );
cmsis_gcc.h:437	__ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
cmsis_gcc.h:459	__ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
cmsis_gcc.h:480	__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
cmsis_gcc.h:497	__ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
cmsis_gcc.h:514	__ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
cmsis_gcc.h:531	__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
cmsis_gcc.h:542	__ASM volatile ("clrex" ::: "memory");
cmsis_gcc.h:597	__ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
cmsis_gcc.h:613	__ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) );
cmsis_gcc.h:635	__ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) );
cmsis_gcc.h:656	__ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) );
cmsis_gcc.h:669	__ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
cmsis_gcc.h:681	__ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
cmsis_gcc.h:693	__ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) );
cmsis_gcc.h:951	__ASM volatile ("cpsie i" : : : "memory");
cmsis_gcc.h:962	__ASM volatile ("cpsid i" : : : "memory");
cmsis_gcc.h:975	__ASM volatile ("MRS %0, control" : "=r" (result) );
cmsis_gcc.h:1003	__ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
cmsis_gcc.h:1031	__ASM volatile ("MRS %0, ipsr" : "=r" (result) );
cmsis_gcc.h:1045	__ASM volatile ("MRS %0, apsr" : "=r" (result) );
cmsis_gcc.h:1059	__ASM volatile ("MRS %0, xpsr" : "=r" (result) );
cmsis_gcc.h:1073	__ASM volatile ("MRS %0, psp" : "=r" (result) );
cmsis_gcc.h:1101	__ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : );
cmsis_gcc.h:1127	__ASM volatile ("MRS %0, msp" : "=r" (result) );
cmsis_gcc.h:1155	__ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : );
cmsis_gcc.h:1208	__ASM volatile ("MRS %0, primask" : "=r" (result) );
cmsis_gcc.h:1236	__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
cmsis_gcc.h:1263	__ASM volatile ("cpsie f" : : : "memory");
cmsis_gcc.h:1274	__ASM volatile ("cpsid f" : : : "memory");
cmsis_gcc.h:1287	__ASM volatile ("MRS %0, basepri" : "=r" (result) );
cmsis_gcc.h:1315	__ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory");
cmsis_gcc.h:1340	__ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory");
cmsis_gcc.h:1353	__ASM volatile ("MRS %0, faultmask" : "=r" (result) );
cmsis_gcc.h:1381	__ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
cmsis_gcc.h:1600	__ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
cmsis_gcc.h:1624	__ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory");
cmsis_gcc.h:1647	__ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
cmsis_gcc.h:1655	__ASM ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
cmsis_gcc.h:1663	__ASM ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
cmsis_gcc.h:1671	__ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
cmsis_gcc.h:1679	__ASM ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
cmsis_gcc.h:1687	__ASM ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
cmsis_gcc.h:1696	__ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
cmsis_gcc.h:1704	__ASM ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
cmsis_gcc.h:1712	__ASM ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
cmsis_gcc.h:1720	__ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
cmsis_gcc.h:1728	__ASM ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
cmsis_gcc.h:1736	__ASM ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
cmsis_gcc.h:1745	__ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
cmsis_gcc.h:1753	__ASM ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
cmsis_gcc.h:1761	__ASM ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
cmsis_gcc.h:1769	__ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
cmsis_gcc.h:1777	__ASM ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
cmsis_gcc.h:1785	__ASM ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
cmsis_gcc.h:1793	__ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
cmsis_gcc.h:1801	__ASM ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
cmsis_gcc.h:1809	__ASM ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
cmsis_gcc.h:1817	__ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
cmsis_gcc.h:1825	__ASM ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
cmsis_gcc.h:1833	__ASM ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
cmsis_gcc.h:1841	__ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
cmsis_gcc.h:1849	__ASM ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
cmsis_gcc.h:1857	__ASM ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
cmsis_gcc.h:1865	__ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
cmsis_gcc.h:1873	__ASM ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
cmsis_gcc.h:1881	__ASM ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
cmsis_gcc.h:1889	__ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
cmsis_gcc.h:1897	__ASM ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
cmsis_gcc.h:1905	__ASM ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
cmsis_gcc.h:1913	__ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
cmsis_gcc.h:1921	__ASM ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
cmsis_gcc.h:1929	__ASM ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
cmsis_gcc.h:1937	__ASM ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
cmsis_gcc.h:1945	__ASM ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
cmsis_gcc.h:1969	__ASM ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
cmsis_gcc.h:1977	__ASM ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
cmsis_gcc.h:1985	__ASM ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
cmsis_gcc.h:1993	__ASM volatile ("sxtb16 %0, %1, ROR %2" : "=r" (result) : "r" (op1), "i" (rotate) );
cmsis_gcc.h:2004	__ASM ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
cmsis_gcc.h:2012	__ASM volatile ("sxtab16 %0, %1, %2, ROR %3" : "=r" (result) : "r" (op1) , "r" (op2) , "i" (rotate));
cmsis_gcc.h:2024	__ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
cmsis_gcc.h:2032	__ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
cmsis_gcc.h:2040	__ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
cmsis_gcc.h:2048	__ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
cmsis_gcc.h:2061	__ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
cmsis_gcc.h:2078	__ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
cmsis_gcc.h:2090	__ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
cmsis_gcc.h:2098	__ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
cmsis_gcc.h:2106	__ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
cmsis_gcc.h:2114	__ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
cmsis_gcc.h:2127	__ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
cmsis_gcc.h:2144	__ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
cmsis_gcc.h:2156	__ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
cmsis_gcc.h:2164	__ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
cmsis_gcc.h:2172	__ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
cmsis_gcc.h:2201	__ASM ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) );

__ASM macro

Syntax

Examples

References