CMSIS
NVIC
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STM32 Libraries and Samples
CMSIS
NVIC
NVIC macro
NVIC configuration struct
Syntax
from
core_cm4.h:1562
#define
NVIC
(
(
NVIC_Type
*
)
NVIC_BASE
)
References
Location
Text
core_cm4.h:1562
#define
NVIC
(
(
NVIC_Type
*
)
NVIC_BASE
)
/*!< NVIC configuration struct */
core_cm4.h:1689
NVIC
->
ISER
[
(
(
(
uint32_t
)
IRQn
)
>
>
5UL
)
]
=
(
uint32_t
)
(
1UL
<
<
(
(
(
uint32_t
)
IRQn
)
&
0x1FUL
)
)
;
core_cm4.h:1707
return
(
(
uint32_t
)
(
(
(
NVIC
->
ISER
[
(
(
(
uint32_t
)
IRQn
)
>
>
5UL
)
]
&
(
1UL
<
<
(
(
(
uint32_t
)
IRQn
)
&
0x1FUL
)
)
)
!=
0UL
)
?
1UL
:
0UL
)
)
;
core_cm4.h:1726
NVIC
->
ICER
[
(
(
(
uint32_t
)
IRQn
)
>
>
5UL
)
]
=
(
uint32_t
)
(
1UL
<
<
(
(
(
uint32_t
)
IRQn
)
&
0x1FUL
)
)
;
core_cm4.h:1745
return
(
(
uint32_t
)
(
(
(
NVIC
->
ISPR
[
(
(
(
uint32_t
)
IRQn
)
>
>
5UL
)
]
&
(
1UL
<
<
(
(
(
uint32_t
)
IRQn
)
&
0x1FUL
)
)
)
!=
0UL
)
?
1UL
:
0UL
)
)
;
core_cm4.h:1764
NVIC
->
ISPR
[
(
(
(
uint32_t
)
IRQn
)
>
>
5UL
)
]
=
(
uint32_t
)
(
1UL
<
<
(
(
(
uint32_t
)
IRQn
)
&
0x1FUL
)
)
;
core_cm4.h:1779
NVIC
->
ICPR
[
(
(
(
uint32_t
)
IRQn
)
>
>
5UL
)
]
=
(
uint32_t
)
(
1UL
<
<
(
(
(
uint32_t
)
IRQn
)
&
0x1FUL
)
)
;
core_cm4.h:1796
return
(
(
uint32_t
)
(
(
(
NVIC
->
IABR
[
(
(
(
uint32_t
)
IRQn
)
>
>
5UL
)
]
&
(
1UL
<
<
(
(
(
uint32_t
)
IRQn
)
&
0x1FUL
)
)
)
!=
0UL
)
?
1UL
:
0UL
)
)
;
core_cm4.h:1818
NVIC
->
IP
[
(
(
uint32_t
)
IRQn
)
]
=
(
uint8_t
)
(
(
priority
<
<
(
8U
-
__NVIC_PRIO_BITS
)
)
&
(
uint32_t
)
0xFFUL
)
;
core_cm4.h:1841
return
(
(
(
uint32_t
)
NVIC
->
IP
[
(
(
uint32_t
)
IRQn
)
]
>
>
(
8U
-
__NVIC_PRIO_BITS
)
)
)
;