target_type::examine is only used within OpenOCD.
 
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target_type::examine field

This method is used to perform target setup that requires JTAG access. This may be called multiple times. It is called after the scan chain is initially validated, or later after the target is enabled by a JRC. It may also be called during some parts of the reset sequence. For one-time initialization tasks, use target_was_examined() and target_set_examined(). For example, probe the hardware before setting up chip-specific state, and then set that flag so you don't do that again.

Syntax

int (*examine)(struct target *target);

References

LocationReferrerScopeText
target_type.h:222
int (*examine)(struct target *target);
aarch64.c:3238aarch64_examine()aarch64_target
aarch64.c:3271
.examine = aarch64_examine,
aarch64.c:3279aarch64_examine()armv8r_target
aarch64.c:3312
.examine = aarch64_examine,
arc.c:2323arc_examine()arcv2_target
arc.c:2368
.examine = arc_examine,
arm11.c:1348arm11_examine()arm11_target
arm11.c:1379
.examine = arm11_examine,
arm720t.c:464arm7_9_examine()arm720t_target
arm720t.c:502
.examine = arm7_9_examine,
arm7tdmi.c:684arm7_9_examine()arm7tdmi_target
arm7tdmi.c:720
.examine = arm7_9_examine,
arm920t.c:1596arm7_9_examine()arm920t_target
arm920t.c:1636
.examine = arm7_9_examine,
arm926ejs.c:790arm7_9_examine()arm926ejs_target
arm926ejs.c:826
.examine = arm7_9_examine,
arm946e.c:738arm7_9_examine()arm946e_target
arm946e.c:779
.examine = arm7_9_examine,
arm966e.c:245arm7_9_examine()arm966e_target
arm966e.c:281
.examine = arm7_9_examine,
arm9tdmi.c:888arm7_9_examine()arm9tdmi_target
arm9tdmi.c:924
.examine = arm7_9_examine,
avr32_ap7k.c:581avr32_ap7k_examine()avr32_ap7k_target
avr32_ap7k.c:610
.examine = avr32_ap7k_examine,
cortex_a.c:3426cortex_a_examine()cortexa_target
cortex_a.c:3465
.examine = cortex_a_examine,
cortex_a.c:3506cortex_a_examine()cortexr4_target
cortex_a.c:3542
.examine = cortex_a_examine,
cortex_m.c:3338cortex_m_examine()cortexm_target
cortex_m.c:3376
.examine = cortex_m_examine,
dsp563xx.c:2250dsp563xx_examine()dsp563xx_target
dsp563xx.c:2281
.examine = dsp563xx_examine,
esirisc.c:1835esirisc_examine()esirisc_target
esirisc.c:1865
.examine = esirisc_examine,
esp32.c:460xtensa_examine()esp32_target
esp32.c:499
.examine = xtensa_examine,
esp32s2.c:497xtensa_examine()esp32s2_target
esp32s2.c:536
.examine = xtensa_examine,
esp32s3.c:381xtensa_examine()esp32s3_target
esp32s3.c:420
.examine = xtensa_examine,
fa526.c:350arm7_9_examine()fa526_target
fa526.c:386
.examine = arm7_9_examine,
feroceon.c:691feroceon_examine()feroceon_target
feroceon.c:727
.examine = feroceon_examine,
feroceon.c:730feroceon_examine()dragonite_target
feroceon.c:765
.examine = feroceon_examine,
hla_target.c:640cortex_m_examine()hla_target
hla_target.c:647
.examine = cortex_m_examine,
mem_ap.c:265mem_ap_examine()mem_ap_target
mem_ap.c:271
.examine = mem_ap_examine,
mips_m4k.c:1467mips_m4k_examine()mips_m4k_target
mips_m4k.c:1497
.examine = mips_m4k_examine,
mips_mips64.c:1151mips_mips64_examine()mips_mips64_target
mips_mips64.c:1183
or1k.c:1417or1k_examine()or1k_target
or1k.c:1447
.examine = or1k_examine,
riscv-011.c:2394examine()riscv011_target
riscv-011.c:2399
.examine = examine,
riscv-013.c:4047examine()riscv013_target
riscv-013.c:4052
.examine = examine,
riscv.c:1143riscv_examine()
return tt->examine(target);
riscv.c:3071riscv_examine()riscv_target
riscv.c:3077
.examine = riscv_examine,
stm8.c:2160stm8_examine()stm8_target
stm8.c:2191
.examine = stm8_examine,
target.c:678target_examine_one()
int retval = target->type->examine(target);
target.c:1492target_init_one()
if (!type->examine)
target.c:1493default_examine()target_init_one()
type->examine = default_examine;
target.c:5396handle_target_examine()
int retval = target->type->examine(target);
xtensa_chip.c:151xtensa_chip_examine()xtensa_chip_target
xtensa_chip.c:190

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