swd_seq_swd_to_jtag - syntax, references, description

SWD-to-JTAG sequence. The SWD-to-JTAG sequence is at least 50 TCK/SWCLK cycles with TMS/SWDIO high, putting either interface logic into reset state, followed by a specific 16-bit sequence and finally at least 5 TCK/SWCLK cycles with TMS/SWDIO high to put the JTAG TAP in Test-Logic-Reset state. Bits are stored (and transmitted) LSB-first.

Syntax

from swd.h:136

static const uint8_t swd_seq_swd_to_jtag[] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x3c, 0xe7, 0xff, };

References

Location	Referrer	Text
swd.h:136		static const uint8_t swd_seq_swd_to_jtag[] = {
adi_v5_jtag.c:728	jtag_send_sequence()	swd_seq_swd_to_jtag, TAP_RESET);
cmsis_dap.c:1263	cmsis_dap_swd_switch_seq()	s = swd_seq_swd_to_jtag;
ftdi.c:1217	ftdi_swd_switch_seq()	mpsse_clock_data_out(mpsse_ctx, swd_seq_swd_to_jtag, 0, swd_seq_swd_to_jtag_len, SWD_MODE);
jlink.c:2131	jlink_swd_switch_seq()	s = swd_seq_swd_to_jtag;
picoprobe.c:449	picoprobe_swd_switch_seq()	ret = picoprobe_write_bits(swd_seq_swd_to_jtag, 0, swd_seq_swd_to_jtag_len);
vsllink.c:728	vsllink_swd_switch_seq()	versaloon_interface.adaptors.swd.seqout(0, swd_seq_swd_to_jtag,