from ![]()
at91sam4.c:74
struct sam4_cfg
{
uint32_t unique_id[4];
uint32_t slow_freq;
uint32_t rc_freq;
uint32_t mainosc_freq;
uint32_t plla_freq;
uint32_t mclk_freq;
uint32_t cpu_freq;
uint32_t fclk_freq;
uint32_t pclk0_freq;
uint32_t pclk1_freq;
uint32_t pclk2_freq;
#define SAM4_CHIPID_CIDR (0x400E0740)
uint32_t CHIPID_CIDR;
#define SAM4_CHIPID_EXID (0x400E0744)
uint32_t CHIPID_EXID;
#define SAM4_PMC_BASE (0x400E0400)
#define SAM4_PMC_SCSR (SAM4_PMC_BASE + 0x0008)
uint32_t PMC_SCSR;
#define SAM4_PMC_PCSR (SAM4_PMC_BASE + 0x0018)
uint32_t PMC_PCSR;
#define SAM4_CKGR_UCKR (SAM4_PMC_BASE + 0x001c)
uint32_t CKGR_UCKR;
#define SAM4_CKGR_MOR (SAM4_PMC_BASE + 0x0020)
uint32_t CKGR_MOR;
#define SAM4_CKGR_MCFR (SAM4_PMC_BASE + 0x0024)
uint32_t CKGR_MCFR;
#define SAM4_CKGR_PLLAR (SAM4_PMC_BASE + 0x0028)
uint32_t CKGR_PLLAR;
#define SAM4_PMC_MCKR (SAM4_PMC_BASE + 0x0030)
uint32_t PMC_MCKR;
#define SAM4_PMC_PCK0 (SAM4_PMC_BASE + 0x0040)
uint32_t PMC_PCK0;
#define SAM4_PMC_PCK1 (SAM4_PMC_BASE + 0x0044)
uint32_t PMC_PCK1;
#define SAM4_PMC_PCK2 (SAM4_PMC_BASE + 0x0048)
uint32_t PMC_PCK2;
#define SAM4_PMC_SR (SAM4_PMC_BASE + 0x0068)
uint32_t PMC_SR;
#define SAM4_PMC_IMR (SAM4_PMC_BASE + 0x006c)
uint32_t PMC_IMR;
#define SAM4_PMC_FSMR (SAM4_PMC_BASE + 0x0070)
uint32_t PMC_FSMR;
#define SAM4_PMC_FSPR (SAM4_PMC_BASE + 0x0074)
uint32_t PMC_FSPR;
};