riscv011_info_t::dcsr - syntax, references, description

References

Location	Referrer	Text
riscv-011.c:184		uint64_t dcsr;
riscv-011.c:1140	execute_resume()	info->dcsr = set_field(info->dcsr, DCSR_EBREAKM, riscv_ebreakm);
riscv-011.c:1141	execute_resume()	info->dcsr = set_field(info->dcsr, DCSR_EBREAKS, riscv_ebreaks);
riscv-011.c:1142	execute_resume()	info->dcsr = set_field(info->dcsr, DCSR_EBREAKU, riscv_ebreaku);
riscv-011.c:1143	execute_resume()	info->dcsr = set_field(info->dcsr, DCSR_EBREAKH, 1);
riscv-011.c:1144	execute_resume()	info->dcsr &= ~DCSR_HALT;
riscv-011.c:1147	execute_resume()	info->dcsr \|= DCSR_STEP;
riscv-011.c:1149	execute_resume()	info->dcsr &= ~DCSR_STEP;
riscv-011.c:1157	execute_resume()	uint64_t dbus_value = DMCONTROL_INTERRUPT \| info->dcsr;
riscv-011.c:1320	register_write()	info->dcsr = set_field(info->dcsr, DCSR_PRV, value);
riscv-011.c:1372	get_register()	*value = get_field(info->dcsr, DCSR_PRV);
riscv-011.c:1819	handle_halt_routine()	info->dcsr = reg_cache_get(target, CSR_DCSR);
riscv-011.c:1844	handle_halt()	int cause = get_field(info->dcsr, DCSR_CAUSE);
riscv-011.c:1861	handle_halt()	cause, info->dcsr);
riscv-011.c:1957	assert_reset()	info->dcsr = set_field(info->dcsr, DCSR_EBREAKM, riscv_ebreakm);
riscv-011.c:1958	assert_reset()	info->dcsr = set_field(info->dcsr, DCSR_EBREAKS, riscv_ebreaks);
riscv-011.c:1959	assert_reset()	info->dcsr = set_field(info->dcsr, DCSR_EBREAKU, riscv_ebreaku);
riscv-011.c:1960	assert_reset()	info->dcsr = set_field(info->dcsr, DCSR_EBREAKH, 1);
riscv-011.c:1961	assert_reset()	info->dcsr \|= DCSR_HALT;
riscv-011.c:1963	assert_reset()	info->dcsr \|= DCSR_NDRESET;
riscv-011.c:1965	assert_reset()	info->dcsr \|= DCSR_FULLRESET;
riscv-011.c:1970	assert_reset()	dram_write32(target, 4, info->dcsr, true);