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dsp563xx.c:222
static const struct {
unsigned id;
const char *name;
unsigned bits;
uint8_t eame;
uint32_t instr_mask;
} dsp563xx_regs[] = {
{DSP563XX_REG_IDX_R0, "r0", 24, 0x10, ASM_REG_W_R0},
{DSP563XX_REG_IDX_R1, "r1", 24, 0x11, ASM_REG_W_R1},
{DSP563XX_REG_IDX_R2, "r2", 24, 0x12, ASM_REG_W_R2},
{DSP563XX_REG_IDX_R3, "r3", 24, 0x13, ASM_REG_W_R3},
{DSP563XX_REG_IDX_R4, "r4", 24, 0x14, ASM_REG_W_R4},
{DSP563XX_REG_IDX_R5, "r5", 24, 0x15, ASM_REG_W_R5},
{DSP563XX_REG_IDX_R6, "r6", 24, 0x16, ASM_REG_W_R6},
{DSP563XX_REG_IDX_R7, "r7", 24, 0x17, ASM_REG_W_R7},
{DSP563XX_REG_IDX_N0, "n0", 24, 0x18, ASM_REG_W_N0},
{DSP563XX_REG_IDX_N1, "n1", 24, 0x19, ASM_REG_W_N1},
{DSP563XX_REG_IDX_N2, "n2", 24, 0x1a, ASM_REG_W_N2},
{DSP563XX_REG_IDX_N3, "n3", 24, 0x1b, ASM_REG_W_N3},
{DSP563XX_REG_IDX_N4, "n4", 24, 0x1c, ASM_REG_W_N4},
{DSP563XX_REG_IDX_N5, "n5", 24, 0x1d, ASM_REG_W_N5},
{DSP563XX_REG_IDX_N6, "n6", 24, 0x1e, ASM_REG_W_N6},
{DSP563XX_REG_IDX_N7, "n7", 24, 0x1f, ASM_REG_W_N7},
{DSP563XX_REG_IDX_M0, "m0", 24, 0x20, ASM_REG_W_M0},
{DSP563XX_REG_IDX_M1, "m1", 24, 0x21, ASM_REG_W_M1},
{DSP563XX_REG_IDX_M2, "m2", 24, 0x22, ASM_REG_W_M2},
{DSP563XX_REG_IDX_M3, "m3", 24, 0x23, ASM_REG_W_M3},
{DSP563XX_REG_IDX_M4, "m4", 24, 0x24, ASM_REG_W_M4},
{DSP563XX_REG_IDX_M5, "m5", 24, 0x25, ASM_REG_W_M5},
{DSP563XX_REG_IDX_M6, "m6", 24, 0x26, ASM_REG_W_M6},
{DSP563XX_REG_IDX_M7, "m7", 24, 0x27, ASM_REG_W_M7},
{DSP563XX_REG_IDX_X0, "x0", 24, 0x04, ASM_REG_W_X0},
{DSP563XX_REG_IDX_X1, "x1", 24, 0x05, ASM_REG_W_X1},
{DSP563XX_REG_IDX_Y0, "y0", 24, 0x06, ASM_REG_W_Y0},
{DSP563XX_REG_IDX_Y1, "y1", 24, 0x07, ASM_REG_W_Y1},
{DSP563XX_REG_IDX_A0, "a0", 24, 0x08, ASM_REG_W_A0},
{DSP563XX_REG_IDX_A1, "a1", 24, 0x0c, ASM_REG_W_A1},
{DSP563XX_REG_IDX_A2, "a2", 8, 0x0a, ASM_REG_W_A2},
{DSP563XX_REG_IDX_B0, "b0", 24, 0x09, ASM_REG_W_B0},
{DSP563XX_REG_IDX_B1, "b1", 24, 0x0d, ASM_REG_W_B1},
{DSP563XX_REG_IDX_B2, "b2", 8, 0x0b, ASM_REG_W_B2},
{DSP563XX_REG_IDX_SSH, "ssh", 24, 0x3c, ASM_REG_W_SSH},
{DSP563XX_REG_IDX_SSL, "ssl", 24, 0x3d, ASM_REG_W_SSL},
{DSP563XX_REG_IDX_SP, "sp", 24, 0x3b, ASM_REG_W_SP},
{DSP563XX_REG_IDX_EP, "ep", 24, 0x2a, ASM_REG_W_EP},
{DSP563XX_REG_IDX_SZ, "sz", 24, 0x38, ASM_REG_W_SZ},
{DSP563XX_REG_IDX_SC, "sc", 24, 0x31, ASM_REG_W_SC},
{DSP563XX_REG_IDX_PC, "pc", 24, 0x00, ASM_REG_W_PC},
{DSP563XX_REG_IDX_SR, "sr", 24, 0x39, ASM_REG_W_SR},
{DSP563XX_REG_IDX_OMR, "omr", 24, 0x3a, ASM_REG_W_OMR},
{DSP563XX_REG_IDX_LA, "la", 24, 0x3e, ASM_REG_W_LA},
{DSP563XX_REG_IDX_LC, "lc", 24, 0x3f, ASM_REG_W_LC},
{DSP563XX_REG_IDX_VBA, "vba", 24, 0x30, ASM_REG_W_VBA},
{DSP563XX_REG_IDX_IPRC, "iprc", 24, 0x00, ASM_REG_W_IPRC},
{DSP563XX_REG_IDX_IPRP, "iprp", 24, 0x00, ASM_REG_W_IPRP},
{DSP563XX_REG_IDX_BCR, "bcr", 24, 0x00, ASM_REG_W_BCR},
{DSP563XX_REG_IDX_DCR, "dcr", 24, 0x00, ASM_REG_W_DCR},
{DSP563XX_REG_IDX_AAR0, "aar0", 24, 0x00, ASM_REG_W_AAR0},
{DSP563XX_REG_IDX_AAR1, "aar1", 24, 0x00, ASM_REG_W_AAR1},
{DSP563XX_REG_IDX_AAR2, "aar2", 24, 0x00, ASM_REG_W_AAR2},
{DSP563XX_REG_IDX_AAR3, "aar3", 24, 0x00, ASM_REG_W_AAR3},
};