OpenOCD
armv7m_common::debug_ap is only used within OpenOCD.
 
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CodeScopeDevelopment ToolsOpenOCDarmv7m_common::debug_ap

armv7m_common::debug_ap field

Syntax

struct adiv5_ap *debug_ap;

References

LocationReferrerText
armv7m.h:230
struct adiv5_ap *debug_ap;
arm_tpiu_swo.c:658handle_arm_tpiu_swo_enable()
obj->spot.ap_num = cm->armv7m.debug_ap->ap_num;
arm_tpiu_swo.c:1065handle_tpiu_deprecated_config_command()
ap_num = cm->armv7m.debug_ap->ap_num;
cortex_m.c:167cortex_m_read_dhcsr_atomic_sticky()
int retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DHCSR,
cortex_m.c:188cortex_m_load_core_reg_u32()
retval = mem_ap_read_u32(armv7m->debug_ap, DCB_DCRDR, &dcrdr);
cortex_m.c:193cortex_m_load_core_reg_u32()
retval = mem_ap_write_u32(armv7m->debug_ap, DCB_DCRSR, regsel);
cortex_m.c:200cortex_m_load_core_reg_u32()
retval = mem_ap_read_u32(armv7m->debug_ap, DCB_DHCSR,
cortex_m.c:204cortex_m_load_core_reg_u32()
retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DCRDR,
cortex_m.c:225cortex_m_load_core_reg_u32()
retval = mem_ap_write_atomic_u32(armv7m->debug_ap, DCB_DCRDR, dcrdr);
cortex_m.c:262cortex_m_queue_reg_read()
retval = mem_ap_write_u32(armv7m->debug_ap, DCB_DCRSR, regsel);
cortex_m.c:266cortex_m_queue_reg_read()
retval = mem_ap_read_u32(armv7m->debug_ap, DCB_DHCSR, dhcsr);
cortex_m.c:270cortex_m_queue_reg_read()
return mem_ap_read_u32(armv7m->debug_ap, DCB_DCRDR, reg_value);
cortex_m.c:284cortex_m_fast_read_all_regs()
retval = mem_ap_read_u32(armv7m->debug_ap, DCB_DCRDR, &dcrdr);
cortex_m.c:332cortex_m_fast_read_all_regs()
retval = dap_run(armv7m->debug_ap->dap);
cortex_m.c:339cortex_m_fast_read_all_regs()
retval = mem_ap_write_atomic_u32(armv7m->debug_ap, DCB_DCRDR, dcrdr);
cortex_m.c:410cortex_m_store_core_reg_u32()
retval = mem_ap_read_u32(armv7m->debug_ap, DCB_DCRDR, &dcrdr);
cortex_m.c:415cortex_m_store_core_reg_u32()
retval = mem_ap_write_u32(armv7m->debug_ap, DCB_DCRDR, value);
cortex_m.c:419cortex_m_store_core_reg_u32()
retval = mem_ap_write_u32(armv7m->debug_ap, DCB_DCRSR, regsel | DCRSR_WNR);
cortex_m.c:442cortex_m_store_core_reg_u32()
retval = mem_ap_write_atomic_u32(armv7m->debug_ap, DCB_DCRDR, dcrdr);
cortex_m.c:459cortex_m_write_debug_halt_mask()
return mem_ap_write_atomic_u32(armv7m->debug_ap, DCB_DHCSR, cortex_m->dcb_dhcsr);
cortex_m.c:549cortex_m_clear_halt()
retval = mem_ap_read_atomic_u32(armv7m->debug_ap, NVIC_DFSR, &cortex_m->nvic_dfsr);
cortex_m.c:554cortex_m_clear_halt()
retval = mem_ap_write_atomic_u32(armv7m->debug_ap, NVIC_DFSR, cortex_m->nvic_dfsr);
cortex_m.c:616cortex_m_endreset_event()
retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DEMCR, &dcb_demcr);
cortex_m.c:622cortex_m_endreset_event()
retval = mem_ap_write_u32(armv7m->debug_ap, DCB_DCRDR, 0);
cortex_m.c:647cortex_m_endreset_event()
retval = mem_ap_write_u32(armv7m->debug_ap, DCB_DEMCR, TRCENA | armv7m->demcr);
cortex_m.c:738cortex_m_examine_exception_reason()
retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_SHCSR, &shcsr);
cortex_m.c:745cortex_m_examine_exception_reason()
retval = mem_ap_read_atomic_u32(armv7m->debug_ap, NVIC_HFSR, &except_sr);
cortex_m.c:749cortex_m_examine_exception_reason()
retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_CFSR, &cfsr);
cortex_m.c:755cortex_m_examine_exception_reason()
retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_CFSR, &except_sr);
cortex_m.c:758cortex_m_examine_exception_reason()
retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_MMFAR, &except_ar);
cortex_m.c:763cortex_m_examine_exception_reason()
retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_CFSR, &except_sr);
cortex_m.c:766cortex_m_examine_exception_reason()
retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_BFAR, &except_ar);
cortex_m.c:771cortex_m_examine_exception_reason()
retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_CFSR, &except_sr);
cortex_m.c:776cortex_m_examine_exception_reason()
retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_SFSR, &except_sr);
cortex_m.c:779cortex_m_examine_exception_reason()
retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_SFAR, &except_ar);
cortex_m.c:786cortex_m_examine_exception_reason()
retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_DFSR, &except_sr);
cortex_m.c:871cortex_m_debug_entry()
retval = mem_ap_read_u32(armv7m->debug_ap, DCB_DSCSR, &dscsr);
cortex_m.c:1249cortex_m_soft_reset_halt()
retval = mem_ap_write_u32(armv7m->debug_ap, DCB_DEMCR,
cortex_m.c:1255cortex_m_soft_reset_halt()
retval = mem_ap_write_atomic_u32(armv7m->debug_ap, NVIC_AIRCR,
cortex_m.c:1267cortex_m_soft_reset_halt()
retval = mem_ap_read_atomic_u32(armv7m->debug_ap, NVIC_DFSR,
cortex_m.c:1756cortex_m_reset_lpc55sx_using_dm_ap()
int retval = dap_lpc55sx_start_debug_session(armv7m->debug_ap->dap);
cortex_m.c:1813cortex_m_reset_lpc55sx()
mem_ap_write_atomic_u32(armv7m->debug_ap, NVIC_AIRCR, AIRCR_VECTKEY | AIRCR_SYSRESETREQ);
cortex_m.c:1861cortex_m_assert_reset()
|| (!armv7m->debug_ap && !target->defer_examine))) {
cortex_m.c:1878cortex_m_assert_reset()
if (!armv7m->debug_ap) {
cortex_m.c:1907cortex_m_assert_reset()
mem_ap_write_u32(armv7m->debug_ap, DCB_DCRDR, 0);
cortex_m.c:1927cortex_m_assert_reset()
retval2 = mem_ap_write_atomic_u32(armv7m->debug_ap, DCB_DEMCR,
cortex_m.c:1966cortex_m_assert_reset()
retval3 = mem_ap_write_atomic_u32(armv7m->debug_ap, NVIC_AIRCR,
cortex_m.c:1972cortex_m_assert_reset()
retval3 = dap_dp_init_or_reconnect(armv7m->debug_ap->dap);
cortex_m.c:1984cortex_m_assert_reset()
mem_ap_read_atomic_u32(armv7m->debug_ap, NVIC_AIRCR, &tmp);
cortex_m.c:2011cortex_m_deassert_reset()
armv7m->debug_ap) {
cortex_m.c:2013cortex_m_deassert_reset()
int retval = dap_dp_init_or_reconnect(armv7m->debug_ap->dap);
cortex_m.c:2403cortex_m_read_memory()
return mem_ap_read_buf(armv7m->debug_ap, buffer, size, count, address);
cortex_m.c:2417cortex_m_write_memory()
return mem_ap_write_buf(armv7m->debug_ap, buffer, size, count, address);
cortex_m.c:2433cortex_m_deinit_target()
if (!armv7m->is_hla_target && armv7m->debug_ap)
cortex_m.c:2434cortex_m_deinit_target()
dap_put_ap(armv7m->debug_ap);
cortex_m.c:2481cortex_m_profiling()
if (armv7m && armv7m->debug_ap) {
cortex_m.c:2486cortex_m_profiling()
retval = mem_ap_read_buf_noincr(armv7m->debug_ap,
cortex_m.c:2748cortex_m_examine()
if (!armv7m->debug_ap) {
cortex_m.c:2751cortex_m_examine()
retval = cortex_m_find_mem_ap(swjdp, &armv7m->debug_ap);
cortex_m.c:2757cortex_m_examine()
armv7m->debug_ap = dap_get_ap(swjdp, cortex_m->apsel);
cortex_m.c:2758cortex_m_examine()
if (!armv7m->debug_ap) {
cortex_m.c:2765cortex_m_examine()
armv7m->debug_ap->memaccess_tck = 8;
cortex_m.c:2767cortex_m_examine()
retval = mem_ap_init(armv7m->debug_ap);
cortex_m.c:2873cortex_m_examine()
armv7m->debug_ap->tar_autoincr_block = (1 << 12);
cortex_m.c:2961cortex_m_dcc_read()
retval = mem_ap_read_buf_noincr(armv7m->debug_ap, buf, 2, 1, DCB_DCRDR);
cortex_m.c:2975cortex_m_dcc_read()
retval = mem_ap_write_buf_noincr(armv7m->debug_ap, buf, 2, 1, DCB_DCRDR);
cortex_m.c:3136handle_cortex_m_vector_catch_command()
retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DEMCR, &demcr);
cortex_m.c:3173handle_cortex_m_vector_catch_command()
retval = mem_ap_write_u32(armv7m->debug_ap, DCB_DEMCR, demcr);
cortex_m.c:3176handle_cortex_m_vector_catch_command()
retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DEMCR, &demcr);
psoc6.c:940handle_reset_halt()
mem_ap_write_atomic_u32(cm->debug_ap, NVIC_AIRCR,
psoc6.c:944handle_reset_halt()
mem_ap_write_atomic_u32(cm->debug_ap, NVIC_AIRCR,
psoc6.c:950handle_reset_halt()
dap_dp_init(cm->debug_ap->dap);
psoc6.c:998psoc6_handle_reset_to_entry()
mem_ap_write_atomic_u32(cm->debug_ap,
psoc6.c:1004psoc6_handle_reset_to_entry()
dap_dp_init(cm->debug_ap->dap);
stm32l4x.c:1743stm32l4_read_idcode()
armv7m->debug_ap && armv7m->debug_ap->ap_num == 1) {
stm32l4x.c:2086stm32l4_probe()
if (armv7m->debug_ap && armv7m->debug_ap->ap_num == 1)

Data Use

Type of armv7m_common::debug_ap
armv7m_common::debug_ap
all items filtered out